[U-Boot] [PATCH v2 3/6] arm: dts: add PCIe controller for MT7623 SoC
Ramon Fried
ramon.fried at gmail.com
Mon Aug 5 08:10:19 UTC 2019
On Mon, Aug 5, 2019 at 10:32 AM Ryder Lee <ryder.lee at mediatek.com> wrote:
> On Mon, 2019-08-05 at 09:34 +0300, Ramon Fried wrote:
> > On Sun, Aug 4, 2019 at 8:26 PM Frank Wunderlich <frank-w at public-files.de>
> wrote:
> > >
> > > From: Ryder Lee <ryder.lee at mediatek.com>
> > >
> > > This adds PCIe and its PHY nodes for MT7623.
> > >
> > > Tested-by: Frank Wunderlich <frank-w at public-files.de>
> > > Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> > > Signed-off-by: Ryder Lee <ryder.lee at mediatek.com>
> > > ---
> > > arch/arm/dts/mt7623.dtsi | 128 +++++++++++++++++++++++
> > > arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 29 +++++
> > > 2 files changed, 157 insertions(+)
> > >
> > > diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
> > > index 64079c61bf..3a868ea2ee 100644
> > > --- a/arch/arm/dts/mt7623.dtsi
> > > +++ b/arch/arm/dts/mt7623.dtsi
> > > @@ -9,6 +9,7 @@
> > > #include <dt-bindings/gpio/gpio.h>
> > > #include <dt-bindings/interrupt-controller/irq.h>
> > > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +#include <dt-bindings/phy/phy.h>
> > > #include <dt-bindings/power/mt7623-power.h>
> > > #include <dt-bindings/reset/mtk-reset.h>
> > > #include "skeleton.dtsi"
> > > @@ -255,6 +256,133 @@
> > > #reset-cells = <1>;
> > > };
> > >
> > > + pcie: pcie at 1a140000 {
> > > + compatible = "mediatek,mt7623-pcie";
> > > + device_type = "pci";
> > > + reg = <0x1a140000 0x1000>, /* PCIe shared registers */
> > > + <0x1a142000 0x1000>, /* Port0 registers */
> > > + <0x1a143000 0x1000>, /* Port1 registers */
> > > + <0x1a144000 0x1000>; /* Port2 registers */
> > > + reg-names = "subsys", "port0", "port1", "port2";
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0xf800 0 0 0>;
> > > + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193
> IRQ_TYPE_LEVEL_LOW>,
> > > + <0x0800 0 0 0 &sysirq GIC_SPI 194
> IRQ_TYPE_LEVEL_LOW>,
> > > + <0x1000 0 0 0 &sysirq GIC_SPI 195
> IRQ_TYPE_LEVEL_LOW>;
> > > + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> > > + <&hifsys CLK_HIFSYS_PCIE0>,
> > > + <&hifsys CLK_HIFSYS_PCIE1>,
> > > + <&hifsys CLK_HIFSYS_PCIE2>;
> > > + clock-names = "free_ck", "sys_ck0", "sys_ck1",
> "sys_ck2";
> > > + resets = <&hifsys HIFSYS_PCIE0_RST>,
> > > + <&hifsys HIFSYS_PCIE1_RST>,
> > > + <&hifsys HIFSYS_PCIE2_RST>;
> > > + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> > > + phys = <&pcie0_port PHY_TYPE_PCIE>,
> > > + <&pcie1_port PHY_TYPE_PCIE>,
> > > + <&u3port1 PHY_TYPE_PCIE>;
> > > + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> > > + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
> > > + bus-range = <0x00 0xff>;
> > > + status = "disabled";
> > > + ranges = <0x81000000 0 0x1a160000 0x1a160000 0
> 0x00010000
> > > + 0x83000000 0 0x60000000 0x60000000 0
> 0x10000000>;
> > > +
> > > + pcie at 0,0 {
> > > + reg = <0x0000 0 0 0 0>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0 0 0 0>;
> > > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193
> IRQ_TYPE_LEVEL_LOW>;
> > > + ranges;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pcie at 1,0 {
> > > + reg = <0x0800 0 0 0 0>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0 0 0 0>;
> > > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194
> IRQ_TYPE_LEVEL_LOW>;
> > > + ranges;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pcie at 2,0 {
> > > + reg = <0x1000 0 0 0 0>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0 0 0 0>;
> > > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195
> IRQ_TYPE_LEVEL_LOW>;
> > > + ranges;
> > > + status = "disabled";
> > > + };
> > > + };
> > > +
> > > + pcie0_phy: pcie-phy at 1a149000 {
> > > + compatible = "mediatek,generic-tphy-v1";
> > > + reg = <0x1a149000 0x0700>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > + status = "disabled";
> > > +
> > > + pcie0_port: pcie-phy at 1a149900 {
> > > + reg = <0x1a149900 0x0700>;
> > > + clocks = <&clk26m>;
> > > + clock-names = "ref";
> > > + #phy-cells = <1>;
> > > + status = "okay";
> > > + };
> > > + };
> > > +
> > > + pcie1_phy: pcie-phy at 1a14a000 {
> > > + compatible = "mediatek,generic-tphy-v1";
> > > + reg = <0x1a14a000 0x0700>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > + status = "disabled";
> > > +
> > > + pcie1_port: pcie-phy at 1a14a900 {
> > > + reg = <0x1a14a900 0x0700>;
> > > + clocks = <&clk26m>;
> > > + clock-names = "ref";
> > > + #phy-cells = <1>;
> > > + status = "okay";
> > > + };
> > > + };
> > > +
> > > + u3phy2: usb-phy at 1a244000 {
> > > + compatible = "mediatek,generic-tphy-v1";
> > > + reg = <0x1a244000 0x0700>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > + status = "disabled";
> > > +
> > > + u2port1: usb-phy at 1a244800 {
> > > + reg = <0x1a244800 0x0100>;
> > > + clocks = <&topckgen CLK_TOP_USB_PHY48M>;
> > > + clock-names = "ref";
> > > + #phy-cells = <1>;
> > > + status = "okay";
> > > + };
> > > +
> > > + u3port1: usb-phy at 1a244900 {
> > > + reg = <0x1a244900 0x0700>;
> > > + clocks = <&clk26m>;
> > > + clock-names = "ref";
> > > + #phy-cells = <1>;
> > > + status = "okay";
> > > + };
> > > + };
> > > +
> > > ethsys: syscon at 1b000000 {
> > > compatible = "mediatek,mt7623-ethsys", "syscon";
> > > reg = <0x1b000000 0x1000>;
> > > diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> > > index 51628bb639..b0c86219b6 100644
> > > --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> > > +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
> > > @@ -172,6 +172,13 @@
> > > };
> > > };
> > >
> > > + pcie_default: pcie-default {
> > > + mux {
> > > + function = "pcie";
> > > + groups = "pcie0_0_perst", "pcie1_0_perst";
> > > + };
> > > + };
> > > +
> > > uart0_pins_a: uart0-default {
> > > mux {
> > > function = "uart";
> > > @@ -201,6 +208,28 @@
> > > };
> > > };
> > >
> > > +&pcie {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pcie_default>;
> > > + status = "okay";
> > > +
> > > + pcie at 0,0 {
> > > + status = "okay";
> > > + };
> > > +
> > > + pcie at 1,0 {
> > > + status = "okay";
> > > + };
> > > +};
> > > +
> > > +&pcie0_phy {
> > > + status = "okay";
> > > +};
> > > +
> > > +&pcie1_phy {
> > > + status = "okay";
> > > +};
> > > +
> > > &uart0 {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&uart0_pins_a>;
> > > --
> > > 2.17.1
> > >
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot at lists.denx.de
> > > https://lists.denx.de/listinfo/u-boot
> >
> > What about dts binding document ?
>
> Is it mandatory? It seems just armada8k has its doc there.
>
It is encouraged.
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