[U-Boot] [PATCH RESEND 11/14] i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz

sbabic at denx.de sbabic at denx.de
Mon Aug 5 18:43:04 UTC 2019

> From: Ye Li <ye.li at nxp.com>
> The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
> set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
> is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
> to workaround the problem. The correct fix should let GPU handle the
> clock rate in kernel.
> Signed-off-by: Ye Li <ye.li at nxp.com>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>

Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de

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