[U-Boot] [PATCH 1/5] arm: dts: sync dts for i.MX6UL
Peng Fan
peng.fan at nxp.com
Tue Aug 6 01:09:50 UTC 2019
> Subject: [PATCH 1/5] arm: dts: sync dts for i.MX6UL
Ping..
Thanks,
Peng.
>
> Sync kernel dts for i.MX6UL from
> commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of
> git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> ---
> arch/arm/dts/imx6ul-14x14-evk.dts | 422 +-----------------------
> arch/arm/dts/imx6ul-14x14-evk.dtsi | 531
> +++++++++++++++++++++++++++++++
> arch/arm/dts/imx6ul-pinfunc.h | 175 +++++-----
> arch/arm/dts/imx6ul.dtsi | 301 ++++++++++++------
> include/dt-bindings/clock/imx6ul-clock.h | 50 +--
> 5 files changed, 863 insertions(+), 616 deletions(-)
> create mode 100644 arch/arm/dts/imx6ul-14x14-evk.dtsi
>
> diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts
> b/arch/arm/dts/imx6ul-14x14-evk.dts
> index a642d77654..2438669f14 100644
> --- a/arch/arm/dts/imx6ul-14x14-evk.dts
> +++ b/arch/arm/dts/imx6ul-14x14-evk.dts
> @@ -1,427 +1,13 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2015 Freescale Semiconductor, Inc.
> - * Copyright 2017-2018 NXP
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2015 Freescale Semiconductor, Inc.
>
> /dts-v1/;
>
> #include "imx6ul.dtsi"
> +#include "imx6ul-14x14-evk.dtsi"
>
> / {
> model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
> compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
> -
> - aliases {
> - spi5 = &soft_spi;
> - };
> -
> - chosen {
> - stdout-path = &uart1;
> - };
> -
> - memory {
> - reg = <0x80000000 0x20000000>;
> - };
> -
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - reg_sd1_vmmc: regulator at 1 {
> - compatible = "regulator-fixed";
> - regulator-name = "VSD_3V3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
> - off-on-delay = <20000>;
> - enable-active-high;
> - };
> -
> - reg_can_3v3: regulator at 0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - regulator-name = "can-3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
> - };
> -
> - reg_gpio_dvfs: regulator-gpio {
> - compatible = "regulator-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_dvfs>;
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1400000>;
> - regulator-name = "gpio_dvfs";
> - regulator-type = "voltage";
> - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
> - states = <1300000 0x1 1400000 0x0>;
> - };
> - };
> -
> - soft_spi: soft-spi {
> - compatible = "spi-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_spi4>;
> - pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> - status = "okay";
> - gpio-sck = <&gpio5 11 0>;
> - gpio-mosi = <&gpio5 10 0>;
> - cs-gpios = <&gpio5 7 0>;
> - num-chipselects = <1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - gpio_spi: gpio_spi at 0 {
> - compatible = "fairchild,74hc595";
> - gpio-controller;
> - #gpio-cells = <2>;
> - reg = <0>;
> - registers-number = <1>;
> - registers-default = /bits/ 8 <0x57>;
> - spi-max-frequency = <100000>;
> - };
> - };
> -};
> -
> -&fec1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_enet1>;
> - phy-mode = "rmii";
> - phy-handle = <ðphy0>;
> - status = "okay";
> -};
> -
> -&fec2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_enet2>;
> - phy-mode = "rmii";
> - phy-handle = <ðphy1>;
> - status = "okay";
> -
> - mdio {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - ethphy0: ethernet-phy at 2 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <2>;
> - };
> -
> - ethphy1: ethernet-phy at 1 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <1>;
> - };
> - };
> -};
> -
> -&i2c1 {
> - clock-frequency = <100000>;
> - pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&pinctrl_i2c1>;
> - pinctrl-1 = <&pinctrl_i2c1_gpio>;
> - scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
> - sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -
> - mag3110 at 0e {
> - compatible = "fsl,mag3110";
> - reg = <0x0e>;
> - position = <2>;
> - };
> -
> - fxls8471 at 1e {
> - compatible = "fsl,fxls8471";
> - reg = <0x1e>;
> - position = <0>;
> - interrupt-parent = <&gpio5>;
> - interrupts = <0 8>;
> - };
> -};
> -
> -&i2c2 {
> - clock_frequency = <100000>;
> - pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&pinctrl_i2c2>;
> - pinctrl-1 = <&pinctrl_i2c2_gpio>;
> - scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
> - sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -};
> -
> -&iomuxc {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_hog_1>;
> - imx6ul-evk {
> - pinctrl_hog_1: hoggrp-1 {
> - fsl,pins = <
> - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /*
> SD1 CD */
> - MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059
> /* SD1 VSELECT */
> - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09
> 0x17059 /* SD1 RESET */
> - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00
> 0x80000000
> - >;
> - };
> -
> - pinctrl_dvfs: dvfsgrp {
> - fsl,pins = <
> - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
> - >;
> - };
> -
> - pinctrl_enet1: enet1grp {
> - fsl,pins = <
> - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00
> 0x1b0b0
> - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01
> 0x1b0b0
> - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00
> 0x1b0b0
> - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01
> 0x1b0b0
> - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
> 0x4001b031
> - >;
> - };
> -
> - pinctrl_enet2: enet2grp {
> - fsl,pins = <
> - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00
> 0x1b0b0
> - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01
> 0x1b0b0
> - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00
> 0x1b0b0
> - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01
> 0x1b0b0
> - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2
> 0x4001b031
> - >;
> - };
> -
> - pinctrl_i2c1: i2c1grp {
> - fsl,pins = <
> - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
> - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
> - >;
> - };
> -
> - pinctrl_i2c1_gpio: i2c1grp_gpio {
> - fsl,pins = <
> - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
> - MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
> - >;
> - };
> -
> - pinctrl_i2c2: i2c2grp {
> - fsl,pins = <
> - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
> - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
> - >;
> - };
> -
> - pinctrl_i2c2_gpio: i2c2grp_gpio {
> - fsl,pins = <
> - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
> - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
> - >;
> - };
> -
> - pinctrl_qspi: qspigrp {
> - fsl,pins = <
> - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
> - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
> - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
> - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
> - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
> - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
> - >;
> - };
> -
> - pinctrl_spi4: spi4grp {
> - fsl,pins = <
> - MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
> - MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
> - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
> - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08
> 0x80000000
> - >;
> - };
> -
> - pinctrl_uart1: uart1grp {
> - fsl,pins = <
> - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX
> 0x1b0b1
> - >;
> - };
> -
> - pinctrl_usb_otg1_id: usbotg1idgrp {
> - fsl,pins = <
> - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID
> 0x17059
> - >;
> - };
> -
> - pinctrl_usdhc1: usdhc1grp {
> - fsl,pins = <
> - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
> - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> - >;
> - };
> -
> - pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> - fsl,pins = <
> - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
> - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
> - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
> - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
> - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
> - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
> - >;
> - };
> -
> - pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> - fsl,pins = <
> - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
> - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
> - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
> - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
> - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
> - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
> - >;
> - };
> -
> - pinctrl_usdhc2: usdhc2grp {
> - fsl,pins = <
> - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
> - MX6UL_PAD_NAND_WE_B__USDHC2_CMD
> 0x17059
> - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> - >;
> - };
> -
> - pinctrl_usdhc2_8bit: usdhc2grp_8bit {
> - fsl,pins = <
> - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
> - MX6UL_PAD_NAND_WE_B__USDHC2_CMD
> 0x17059
> - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
> - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
> - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
> - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
> - >;
> - };
> -
> - pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
> - fsl,pins = <
> - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
> - MX6UL_PAD_NAND_WE_B__USDHC2_CMD
> 0x170b9
> - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
> - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
> - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
> - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
> - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
> - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
> - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
> - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
> - >;
> - };
> -
> - pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
> - fsl,pins = <
> - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
> - MX6UL_PAD_NAND_WE_B__USDHC2_CMD
> 0x170f9
> - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
> - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
> - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
> - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
> - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
> - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
> - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
> - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
> - >;
> - };
> - pinctrl_wdog: wdoggrp {
> - fsl,pins = <
> - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY
> 0x30b0
> - >;
> - };
> - };
> -};
> -
> -&qspi {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_qspi>;
> - status = "okay";
> - ddrsmp=<0>;
> -
> - flash0: n25q256a at 0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "micron,n25q256a";
> - spi-max-frequency = <29000000>;
> - spi-nor,ddr-quad-read-dummy = <6>;
> - reg = <0>;
> - };
> -};
> -
> -&uart1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart1>;
> - status = "okay";
> -};
> -
> -&usbotg1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_usb_otg1_id>;
> - dr_mode = "otg";
> - srp-disable;
> - hnp-disable;
> - adp-disable;
> - status = "okay";
> -};
> -
> -&usbotg2 {
> - dr_mode = "host";
> - disable-over-current;
> - status = "okay";
> -};
> -
> -&usbphy1 {
> - tx-d-cal = <0x5>;
> -};
> -
> -&usbphy2 {
> - tx-d-cal = <0x5>;
> -};
> -
> -&usdhc1 {
> - pinctrl-names = "default", "state_100mhz", "state_200mhz";
> - pinctrl-0 = <&pinctrl_usdhc1>;
> - pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> - pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> - keep-power-in-suspend;
> - wakeup-source;
> - vmmc-supply = <®_sd1_vmmc>;
> - status = "okay";
> -};
> -
> -&usdhc2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_usdhc2>;
> - non-removable;
> - status = "okay";
> -};
> -
> -&wdog1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_wdog>;
> - fsl,ext-reset-output;
> };
> diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi
> b/arch/arm/dts/imx6ul-14x14-evk.dtsi
> new file mode 100644
> index 0000000000..d1baf0f081
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi
> @@ -0,0 +1,531 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2015 Freescale Semiconductor, Inc.
> +
> +/ {
> + aliases {
> + spi5 = &{/spi4};
> + };
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + backlight_display: backlight-display {
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +
> +
> + reg_sd1_vmmc: regulator-sd1-vmmc {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_can_3v3: regulator-can-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "can-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
> + };
> +
> + spi4 {
> + compatible = "spi-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi4>;
> + status = "okay";
> + gpio-sck = <&gpio5 11 0>;
> + gpio-mosi = <&gpio5 10 0>;
> + cs-gpios = <&gpio5 7 0>;
> + num-chipselects = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio_spi: gpio at 0 {
> + compatible = "fairchild,74hc595";
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0>;
> + registers-number = <1>;
> + spi-max-frequency = <100000>;
> + };
> + };
> +
> + panel {
> + compatible = "innolux,at043tn24";
> + backlight = <&backlight_display>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&display_out>;
> + };
> + };
> + };
> +};
> +
> +&clks {
> + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
> + assigned-clock-rates = <786432000>;
> +};
> +
> +&i2c2 {
> + clock_frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + codec: wm8960 at 1a {
> + #sound-dai-cells = <0>;
> + compatible = "wlf,wm8960";
> + reg = <0x1a>;
> + wlf,shared-lrclk;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy0>;
> + status = "okay";
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy1>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy at 2 {
> + reg = <2>;
> + micrel,led-mode = <1>;
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + clock-names = "rmii-ref";
> + };
> +
> + ethphy1: ethernet-phy at 1 {
> + reg = <1>;
> + micrel,led-mode = <1>;
> + clocks = <&clks IMX6UL_CLK_ENET2_REF>;
> + clock-names = "rmii-ref";
> + };
> + };
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + xceiver-supply = <®_can_3v3>;
> + status = "okay";
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + xceiver-supply = <®_can_3v3>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + pinctrl-1 = <&pinctrl_i2c1_gpio>;
> + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + mag3110 at e {
> + compatible = "fsl,mag3110";
> + reg = <0x0e>;
> + };
> +};
> +
> +&lcdif {
> + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
> + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat
> + &pinctrl_lcdif_ctrl>;
> + status = "okay";
> +
> + port {
> + display_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + flash0: n25q256a at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "micron,n25q256a";
> + spi-max-frequency = <29000000>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <4>;
> + reg = <0>;
> + };
> +};
> +
> +&sai2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai2>;
> + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
> + <&clks IMX6UL_CLK_SAI2>;
> + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
> + assigned-clock-rates = <0>, <12288000>;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&tsc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_tsc>;
> + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> + measure-delay-time = <0xffff>;
> + pre-charge-time = <0xfff>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usbphy1 {
> + fsl,tx-d-cal = <106>;
> +};
> +
> +&usbphy2 {
> + fsl,tx-d-cal = <106>;
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_sd1_vmmc>;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + wakeup-source;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + pinctrl_csi1: csi1grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
> + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
> + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
> + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
> + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
> + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
> + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
> + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
> + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
> + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
> + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
> + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
> + >;
> + };
> +
> + pinctrl_enet1: enet1grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
> 0x4001b031
> + >;
> + };
> +
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2
> 0x4001b031
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp{
> + fsl,pins = <
> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp{
> + fsl,pins = <
> + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
> + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c1_gpio: i2c1grp_gpio {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
> + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
> + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + /* used for lcd reset */
> + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
> + >;
> + };
> +
> + pinctrl_qspi: qspigrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
> + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
> + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
> + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
> + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
> + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
> + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
> + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_sim2: sim2grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
> + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
> + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B
> 0xb808
> + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
> + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
> + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
> + >;
> + };
> +
> + pinctrl_spi4: spi4grp {
> + fsl,pins = <
> + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
> + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
> + >;
> + };
> +
> + pinctrl_tsc: tscgrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
> + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
> /* SD1 CD */
> + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059
> /* SD1 VSELECT */
> + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /*
> SD1 RESET */
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
> +
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
> + >;
> + };
> +};
> diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h
> index 0034eeb845..380d2db13a 100644
> --- a/arch/arm/dts/imx6ul-pinfunc.h
> +++ b/arch/arm/dts/imx6ul-pinfunc.h
> @@ -1,10 +1,6 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> /*
> - * Copyright (C) 2015 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> + * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
> */
>
> #ifndef __DTS_IMX6UL_PINFUNC_H
> @@ -34,14 +30,14 @@
> #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044
> 0x02d0 0x0000 3 0
> #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044
> 0x02d0 0x04c0 4 0
> #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044
> 0x02d0 0x0000 5 0
> -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044
> 0x02d0 0x0000 6 0
> +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044
> 0x02d0 0x0610 6 0
> #define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4
> 0x0000 0 0
> #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048
> 0x02d4 0x0598 1 0
> -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4
> 0x0000 2 0
> +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4
> 0x05f0 2 0
> #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048
> 0x02d4 0x0000 3 0
> #define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4
> 0x0000 4 0
> #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048
> 0x02d4 0x0000 5 0
> -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048
> 0x02d4 0x0000 6 0
> +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048
> 0x02d4 0x0614 6 0
> #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4
> 0x0000 8 0
> #define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8
> 0x0000 0 0
> #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c
> 0x02d8 0x059c 1 0
> @@ -63,12 +59,14 @@
> #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0
> 0x05f4 2 0
> #define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0
> 0x0000 4 0
> #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0
> 0x0000 5 0
> +#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054
> 0x02e0 0x0000 6 0
> #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054
> 0x02e0 0x0000 8 0
> #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4
> 0x0000 0 0
> #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058
> 0x02e4 0x0000 1 0
> #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058
> 0x02e4 0x0000 2 0
> #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058
> 0x02e4 0x0000 4 0
> #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4
> 0x0000 5 0
> +#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058
> 0x02e4 0x0000 6 0
> #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058
> 0x02e4 0x0000 8 0
> #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8
> 0x05ac 0 1
> #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c
> 0x02e8 0x058c 1 0
> @@ -94,22 +92,24 @@
> #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064
> 0x02f0 0x0000 3 0
> #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0
> 0x066c 4 0
> #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0
> 0x0000 5 0
> -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064
> 0x02f0 0x0000 6 0
> +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064
> 0x02f0 0x0610 6 1
> #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064
> 0x02f0 0x0000 7 0
> #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0
> 0x0000 8 0
> #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0
> 0x0624 8 0
> #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4
> 0x05a8 0 1
> #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4
> 0x0000 1 0
> #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4
> 0x0660 2 0
> +#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4
> 0x0000 3 0
> #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4
> 0x0668 4 0
> #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4
> 0x0000 5 0
> -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4
> 0x0000 6 0
> +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4
> 0x0000 6 0
> #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4
> 0x0000 7 0
> -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4
> 0x0000 8 0
> #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4
> 0x0624 8 1
> +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4
> 0x0000 8 0
> #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8
> 0x0574 0 1
> #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8
> 0x0000 1 0
> #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8
> 0x0000 2 0
> +#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8
> 0x0000 3 0
> #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8
> 0x0000 4 0
> #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8
> 0x0000 5 0
> #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c
> 0x02f8 0x0000 6 0
> @@ -200,7 +200,7 @@
> #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094
> 0x0320 0x04dc 3 0
> #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094
> 0x0320 0x058c 4 1
> #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094
> 0x0320 0x0000 5 0
> -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094
> 0x0320 0x0000 8 0
> +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094
> 0x0320 0x0560 8 0
> #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098
> 0x0324 0x062c 0 1
> #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098
> 0x0324 0x0000 0 0
> #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098
> 0x0324 0x0000 1 0
> @@ -232,7 +232,7 @@
> #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4
> 0x0330 0x0634 0 0
> #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4
> 0x0330 0x0000 1 0
> #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4
> 0x0330 0x0000 2 0
> -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4
> 0x0330 0x0000 3 0
> +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4
> 0x0330 0x04d4 3 0
> #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4
> 0x0330 0x0000 4 0
> #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4
> 0x0330 0x0628 4 2
> #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4
> 0x0330 0x0000 5 0
> @@ -242,7 +242,7 @@
> #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8
> 0x0334 0x0000 0 0
> #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8
> 0x0334 0x0000 1 0
> #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8
> 0x0334 0x0000 2 0
> -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8
> 0x0334 0x0000 3 0
> +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8
> 0x0334 0x04d0 3 0
> #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8
> 0x0334 0x0628 4 3
> #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8
> 0x0334 0x0000 4 0
> #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8
> 0x0334 0x0000 5 0
> @@ -251,7 +251,7 @@
> #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac
> 0x0338 0x0630 0 0
> #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac
> 0x0338 0x0000 1 0
> #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac
> 0x0338 0x0000 2 0
> -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338
> 0x0000 3 0
> +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338
> 0x04ec 3 0
> #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac
> 0x0338 0x0000 4 0
> #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338
> 0x0000 5 0
> #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338
> 0x0000 8 0
> @@ -259,7 +259,7 @@
> #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0
> 0x033c 0x0000 0 0
> #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0
> 0x033c 0x0000 1 0
> #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0
> 0x033c 0x0584 2 0
> -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c
> 0x0000 3 0
> +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c
> 0x04f0 3 0
> #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT
> 0x00b0 0x033c 0x0000 4 0
> #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c
> 0x0000 5 0
> #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0
> 0x033c 0x0000 8 0
> @@ -267,7 +267,7 @@
> #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4
> 0x0340 0x063c 0 0
> #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4
> 0x0340 0x0000 1 0
> #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340
> 0x05a4 2 1
> -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4
> 0x0340 0x0000 3 0
> +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4
> 0x0340 0x04f4 3 0
> #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02
> 0x00b4 0x0340 0x0000 4 0
> #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4
> 0x0340 0x0000 5 0
> #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4
> 0x0340 0x0544 8 1
> @@ -275,23 +275,23 @@
> #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8
> 0x0344 0x0000 0 0
> #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8
> 0x0344 0x0000 1 0
> #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344
> 0x05a8 2 2
> -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8
> 0x0344 0x0000 3 0
> +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8
> 0x0344 0x04f8 3 0
> #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01
> 0x00b8 0x0344 0x0000 4 0
> #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8
> 0x0344 0x0000 5 0
> -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8
> 0x0344 0x0000 8 0
> +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8
> 0x0344 0x0550 8 1
> #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc
> 0x0348 0x0000 5 0
> #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc
> 0x0348 0x054c 8 0
> #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc
> 0x0348 0x0000 0 0
> #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc
> 0x0348 0x0644 0 4
> #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc
> 0x0348 0x0000 1 0
> #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348
> 0x05ac 2 2
> -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc
> 0x0348 0x0000 3 0
> +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc
> 0x0348 0x04fc 3 0
> #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00
> 0x00bc 0x0348 0x0000 4 0
> #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0
> 0x034c 0x0644 0 5
> #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0
> 0x034c 0x0000 0 0
> #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0
> 0x034c 0x0000 1 0
> #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c
> 0x05b0 2 2
> -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0
> 0x034c 0x0000 3 0
> +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0
> 0x034c 0x0500 3 0
> #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0
> 0x034c 0x0000 4 0
> #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0
> 0x034c 0x0000 5 0
> #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0
> 0x034c 0x0548 8 1
> @@ -299,59 +299,61 @@
> #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4
> 0x0350 0x0638 1 0
> #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4
> 0x0350 0x0000 1 0
> #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4
> 0x0350 0x0000 2 0
> -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4
> 0x0350 0x0000 3 0
> +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4
> 0x0350 0x0504 3 0
> #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4
> 0x0350 0x0000 4 0
> #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4
> 0x0350 0x0000 5 0
> -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4
> 0x0350 0x0000 6 0
> +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4
> 0x0350 0x05d0 6 0
> #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4
> 0x0350 0x0000 8 0
> #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8
> 0x0354 0x0000 0 0
> #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8
> 0x0354 0x0000 1 0
> #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8
> 0x0354 0x0638 1 1
> #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8
> 0x0354 0x0000 2 0
> -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8
> 0x0354 0x0000 3 0
> +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8
> 0x0354 0x0508 3 0
> #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8
> 0x0354 0x0584 4 1
> #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8
> 0x0354 0x0000 5 0
> -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8
> 0x0354 0x0000 6 0
> +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8
> 0x0354 0x05c4 6 0
> #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8
> 0x0354 0x0000 8 0
> #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc
> 0x0358 0x0000 0 0
> #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc
> 0x0358 0x0640 1 3
> #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc
> 0x0358 0x0000 1 0
> -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358
> 0x0000 3 0
> +#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc
> 0x0358 0x0000 2 0
> +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358
> 0x050c 3 0
> #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc
> 0x0358 0x0000 4 0
> #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358
> 0x0000 5 0
> -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358
> 0x0000 6 0
> +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358
> 0x05d4 6 0
> #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc
> 0x0358 0x0000 8 0
> #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0
> 0x035c 0x0000 0 0
> #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0
> 0x035c 0x0000 1 0
> #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0
> 0x035c 0x0640 1 4
> -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0
> 0x035c 0x0000 3 0
> +#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0
> 0x035c 0x0000 2 0
> +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0
> 0x035c 0x0510 3 0
> #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0
> 0x035c 0x0588 4 1
> #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0
> 0x035c 0x0000 5 0
> -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0
> 0x035c 0x0000 6 0
> +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0
> 0x035c 0x05c8 6 0
> #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0
> 0x035c 0x0000 8 0
> #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4
> 0x0360 0x0000 0 0
> #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4
> 0x0360 0x0000 1 0
> #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4
> 0x0360 0x0648 1 2
> #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4
> 0x0360 0x0000 2 0
> -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4
> 0x0360 0x0000 3 0
> +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4
> 0x0360 0x0514 3 0
> #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4
> 0x0360 0x0580 4 1
> #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4
> 0x0360 0x0000 5 0
> -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4
> 0x0360 0x0000 6 0
> +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4
> 0x0360 0x05d8 6 0
> #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB
> 0x00d4 0x0360 0x0000 8 0
> #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8
> 0x0364 0x0000 0 0
> #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8
> 0x0364 0x0648 1 3
> #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8
> 0x0364 0x0000 1 0
> #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8
> 0x0364 0x0000 2 0
> -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364
> 0x0000 3 0
> +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364
> 0x0518 3 0
> #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364
> 0x0000 4 0
> #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364
> 0x0000 5 0
> -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364
> 0x0000 6 0
> +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364
> 0x05cc 6 0
> #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB
> 0x00d8 0x0364 0x0000 8 0
> #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc
> 0x0368 0x0000 0 0
> #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc
> 0x0368 0x0000 1 0
> #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc
> 0x0368 0x0650 1 0
> #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc
> 0x0368 0x0000 2 0
> -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368
> 0x0000 3 0
> +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368
> 0x051c 3 0
> #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc
> 0x0368 0x0574 4 2
> #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc
> 0x0368 0x0000 5 0
> #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc
> 0x0368 0x0000 6 0
> @@ -360,7 +362,7 @@
> #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0
> 0x036c 0x0650 1 1
> #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0
> 0x036c 0x0000 1 0
> #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0
> 0x036c 0x0000 2 0
> -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c
> 0x0000 3 0
> +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c
> 0x0520 3 0
> #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0
> 0x036c 0x0000 4 0
> #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c
> 0x0000 5 0
> #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c
> 0x0000 6 0
> @@ -377,7 +379,7 @@
> #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8
> 0x0374 0x0000 0 0
> #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8
> 0x0374 0x064c 1 2
> #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8
> 0x0374 0x0000 1 0
> -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8
> 0x0374 0x0000 2 0
> +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8
> 0x0374 0x0000 2 0
> #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8
> 0x0374 0x05b8 3 1
> #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8
> 0x0374 0x0000 4 0
> #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8
> 0x0374 0x0000 5 0
> @@ -400,6 +402,7 @@
> #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c
> 0x0000 4 0
> #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c
> 0x0000 5 0
> #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c
> 0x0000 6 0
> +#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0
> 0x037c 0x0000 8 0
> #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4
> 0x0380 0x0000 0 0
> #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4
> 0x0380 0x0000 1 0
> #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4
> 0x0380 0x065c 1 0
> @@ -412,7 +415,7 @@
> #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384
> 0x0000 0 0
> #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384
> 0x065c 1 1
> #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384
> 0x0000 1 0
> -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384
> 0x0000 2 0
> +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8
> 0x0384 0x0000 2 0
> #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384
> 0x056c 3 0
> #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8
> 0x0384 0x0000 4 0
> #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384
> 0x0000 5 0
> @@ -431,7 +434,7 @@
> #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100
> 0x038c 0x0658 1 1
> #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100
> 0x038c 0x0000 1 0
> #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100
> 0x038c 0x0000 2 0
> -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c
> 0x0000 3 0
> +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c
> 0x0570 3 0
> #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100
> 0x038c 0x0000 4 0
> #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c
> 0x0000 5 0
> #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c
> 0x0000 6 0
> @@ -440,7 +443,7 @@
> #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104
> 0x0390 0x0000 1 0
> #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104
> 0x0390 0x0000 2 0
> #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104
> 0x0390 0x063c 2 2
> -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390
> 0x0600 3 0
> #define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390
> 0x0000 4 0
> #define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390
> 0x0000 5 0
> #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB
> 0x0104 0x0390 0x0000 8 0
> @@ -464,7 +467,7 @@
> #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110
> 0x039c 0x05dc 1 1
> #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110
> 0x039c 0x0638 2 3
> #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110
> 0x039c 0x0000 2 0
> -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c
> 0x0604 3 0
> #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110
> 0x039c 0x0000 4 0
> #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110
> 0x039c 0x0000 5 0
> #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110
> 0x039c 0x0000 8 0
> @@ -477,13 +480,15 @@
> #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114
> 0x03a0 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118
> 0x03a4 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118
> 0x03a4 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118
> 0x03a4 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4
> 0x05b8 4 2
> #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118
> 0x03a4 0x0000 6 0
> -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118
> 0x03a4 0x0000 8 0
> +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118
> 0x03a4 0x05e0 8 1
> #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c
> 0x03a8 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c
> 0x03a8 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c
> 0x03a8 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8
> 0x05b4 4 2
> #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8
> 0x0000 5 0
> @@ -491,6 +496,7 @@
> #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c
> 0x03a8 0x05ec 8 0
> #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120
> 0x03ac 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120
> 0x03ac 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120
> 0x03ac 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac
> 0x05c0 4 2
> #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac
> 0x0000 5 0
> @@ -498,14 +504,16 @@
> #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac
> 0x05e8 8 0
> #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124
> 0x03b0 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124
> 0x03b0 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124
> 0x03b0 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0
> 0x05bc 4 2
> #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124
> 0x03b0 0x0000 6 0
> -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0
> 0x0000 8 0
> +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0
> 0x05e4 8 0
> #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128
> 0x03b4 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128
> 0x03b4 0x0658 1 2
> +#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128
> 0x03b4 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128
> 0x03b4 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4
> 0x0000 5 0
> @@ -514,6 +522,7 @@
> #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c
> 0x03b8 0x0658 1 3
> #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c
> 0x03b8 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c
> 0x03b8 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c
> 0x03b8 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c
> 0x03b8 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8
> 0x0000 5 0
> @@ -522,6 +531,7 @@
> #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130
> 0x03bc 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130
> 0x03bc 0x0650 1 2
> +#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130
> 0x03bc 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130
> 0x03bc 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc
> 0x0000 5 0
> @@ -530,6 +540,7 @@
> #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134
> 0x03c0 0x0650 1 3
> #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134
> 0x03c0 0x0000 1 0
> +#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134
> 0x03c0 0x0000 2 0
> #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134
> 0x03c0 0x0000 3 0
> #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134
> 0x03c0 0x061c 4 0
> #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0
> 0x0000 5 0
> @@ -537,56 +548,64 @@
> #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0
> 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4
> 0x0618 1 2
> -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138
> 0x03c4 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4
> 0x0504 3 1
> #define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138
> 0x03c4 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4
> 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8
> 0x0000 0 0
> -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c
> 0x03c8 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c
> 0x03c8 0x0600 1 1
> +#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c
> 0x03c8 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8
> 0x0508 3 1
> #define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c
> 0x03c8 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8
> 0x0584 8 2
> #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140
> 0x03cc 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140
> 0x03cc 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc
> 0x050c 3 1
> #define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140
> 0x03cc 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc
> 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0
> 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144
> 0x03d0 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0
> 0x0510 3 1
> #define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144
> 0x03d0 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0
> 0x0588 8 2
> #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148
> 0x03d4 0x060c 1 1
> -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148
> 0x03d4 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4
> 0x0514 3 1
> #define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148
> 0x03d4 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4
> 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8
> 0x0608 1 1
> -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c
> 0x03d8 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8
> 0x0518 3 1
> #define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c
> 0x03d8 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c
> 0x03d8 0x0000 8 0
> #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc
> 0x0000 0 0
> -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc
> 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc
> 0x0604 1 1
> +#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150
> 0x03dc 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc
> 0x051c 3 1
> #define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150
> 0x03dc 0x0000 6 0
> #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150
> 0x03dc 0x068c 8 0
> #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0
> 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154
> 0x03e0 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0
> 0x0520 3 1
> #define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154
> 0x03e0 0x0000 6 0
> @@ -594,7 +613,8 @@
> #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158
> 0x03e4 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158
> 0x03e4 0x0654 1 2
> -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158
> 0x03e4 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4
> 0x04d4 3 1
> #define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158
> 0x03e4 0x0000 6 0
> @@ -602,7 +622,8 @@
> #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c
> 0x03e8 0x0654 1 3
> #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c
> 0x03e8 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c
> 0x03e8 0x0000 2 0
> +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8
> 0x04d0 3 1
> #define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c
> 0x03e8 0x0000 6 0
> @@ -610,7 +631,7 @@
> #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160
> 0x03ec 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160
> 0x03ec 0x0000 2 0
> -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec
> 0x04ec 3 1
> #define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160
> 0x03ec 0x0000 6 0
> @@ -622,7 +643,7 @@
> #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0
> 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164
> 0x03f0 0x0000 2 0
> -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0
> 0x04f0 3 1
> #define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4
> 0x0000 6 0
> @@ -631,12 +652,12 @@
> #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4
> 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4
> 0x065c 1 2
> #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4
> 0x0534 2 0
> -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4
> 0x04f4 3 1
> #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8
> 0x065c 1 3
> #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8
> 0x0000 1 0
> -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8
> 0x0000 2 0
> -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8
> 0x0540 2 0
> +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8
> 0x04f8 3 1
> #define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8
> 0x0000 6 0
> @@ -644,7 +665,7 @@
> #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc
> 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc
> 0x053c 2 0
> -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc
> 0x04fc 3 1
> #define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc
> 0x0000 6 0
> @@ -652,7 +673,7 @@
> #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400
> 0x0000 0 0
> #define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174
> 0x0400 0x0000 1 0
> #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400
> 0x0538 2 0
> -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400
> 0x0000 3 0
> +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400
> 0x0500 3 1
> #define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400
> 0x0000 4 0
> #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400
> 0x0000 5 0
> #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174
> 0x0400 0x0000 6 0
> @@ -660,42 +681,42 @@
> #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178
> 0x0404 0x0000 0 0
> #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178
> 0x0404 0x0670 1 2
> #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404
> 0x0000 2 0
> -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178
> 0x0404 0x0000 3 0
> +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178
> 0x0404 0x05d0 3 1
> #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178
> 0x0404 0x0000 4 0
> #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178
> 0x0404 0x0000 5 0
> #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178
> 0x0404 0x0000 8 0
> #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c
> 0x0408 0x0000 0 0
> #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c
> 0x0408 0x0678 1 2
> #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c
> 0x0408 0x0000 2 0
> -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c
> 0x0408 0x0000 3 0
> +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c
> 0x0408 0x05c4 3 1
> #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c
> 0x0408 0x0000 4 0
> #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c
> 0x0408 0x0000 5 0
> #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c
> 0x0408 0x0000 8 0
> #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180
> 0x040c 0x0000 0 0
> #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180
> 0x040c 0x067c 1 2
> #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180
> 0x040c 0x0000 2 0
> -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c
> 0x0000 3 0
> +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180
> 0x040c 0x05d4 3 1
> #define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180
> 0x040c 0x0000 4 0
> #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180
> 0x040c 0x0000 5 0
> #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c
> 0x0000 8 0
> #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184
> 0x0410 0x0000 0 0
> #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184
> 0x0410 0x0680 1 2
> #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184
> 0x0410 0x0000 2 0
> -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410
> 0x0000 3 0
> +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410
> 0x05c8 3 1
> #define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184
> 0x0410 0x0000 4 0
> #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184
> 0x0410 0x0000 5 0
> #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410
> 0x0000 8 0
> #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188
> 0x0414 0x0000 0 0
> #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188
> 0x0414 0x0684 1 1
> #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188
> 0x0414 0x0000 2 0
> -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414
> 0x0000 3 0
> +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188
> 0x0414 0x05d8 3 1
> #define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188
> 0x0414 0x0000 4 0
> #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188
> 0x0414 0x0000 5 0
> #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414
> 0x0000 8 0
> #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c
> 0x0418 0x0000 0 0
> #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c
> 0x0418 0x0688 1 2
> #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c
> 0x0418 0x0000 2 0
> -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418
> 0x0000 3 0
> +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418
> 0x05cc 3 1
> #define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c
> 0x0418 0x0000 4 0
> #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c
> 0x0418 0x0000 5 0
> #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418
> 0x0000 8 0
> @@ -726,7 +747,7 @@
> #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c
> 0x0428 0x0000 0 0
> #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c
> 0x0428 0x0698 1 1
> #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c
> 0x0428 0x0000 2 0
> -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428
> 0x0000 3 0
> +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428
> 0x0570 3 1
> #define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c
> 0x0428 0x0000 4 0
> #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c
> 0x0428 0x0000 5 0
> #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c
> 0x0428 0x0628 8 5
> @@ -748,7 +769,7 @@
> #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B
> 0x01a8 0x0434 0x0000 0 0
> #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8
> 0x0434 0x0000 1 0
> #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8
> 0x0434 0x0000 2 0
> -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8
> 0x0434 0x0000 3 0
> +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8
> 0x0434 0x0560 3 1
> #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8
> 0x0434 0x0000 4 0
> #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8
> 0x0434 0x0000 5 0
> #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8
> 0x0434 0x0000 8 0
> @@ -783,7 +804,7 @@
> #define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8
> 0x0444 0x0000 3 0
> #define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444
> 0x0000 4 0
> #define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8
> 0x0444 0x0000 5 0
> -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8
> 0x0444 0x0000 6 0
> +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8
> 0x0444 0x0614 6 1
> #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444
> 0x061c 8 1
> #define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc
> 0x0448 0x0000 0 0
> #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc
> 0x0448 0x0000 1 0
> @@ -791,11 +812,11 @@
> #define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448
> 0x0000 3 0
> #define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc
> 0x0448 0x0000 4 0
> #define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448
> 0x0000 5 0
> -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc
> 0x0448 0x0000 6 0
> +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc
> 0x0448 0x0610 6 2
> #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc
> 0x0448 0x0000 8 0
> #define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c
> 0x0000 0 0
> #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c
> 0x0000 1 0
> -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c
> 0x0000 2 0
> +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c
> 0x05f0 2 1
> #define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c
> 0x0618 3 3
> #define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c
> 0x0000 4 0
> #define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c
> 0x0000 5 0
> @@ -878,10 +899,10 @@
> #define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474
> 0x04c8 0 0
> #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8
> 0x0474 0x0680 1 0
> #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8
> 0x0474 0x0000 2 0
> -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474
> 0x0000 3 0
> +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474
> 0x0550 3 0
> #define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8
> 0x0474 0x0000 4 0
> #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474
> 0x0000 5 0
> -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8
> 0x0474 0x0000 6 0
> +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8
> 0x0474 0x05e0 6 0
> #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8
> 0x0474 0x0644 8 1
> #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8
> 0x0474 0x0000 8 0
> #define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478
> 0x04d8 0 1
> @@ -913,7 +934,7 @@
> #define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484
> 0x04e0 0 1
> #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484
> 0x0690 1 2
> #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8
> 0x0484 0x0000 2 0
> -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484
> 0x0000 3 0
> +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484
> 0x0540 3 1
> #define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484
> 0x0000 4 0
> #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484
> 0x0000 5 0
> #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484
> 0x05e8 6 1
> @@ -924,7 +945,7 @@
> #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488
> 0x053c 3 1
> #define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488
> 0x0000 4 0
> #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488
> 0x0000 5 0
> -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488
> 0x0000 6 0
> +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488
> 0x05e4 6 1
> #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488
> 0x0000 8 0
> #define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c
> 0x04e8 0 1
> #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200
> 0x048c 0x0698 1 2
> diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
> index 71b42d4a20..5644b0f34d 100644
> --- a/arch/arm/dts/imx6ul.dtsi
> +++ b/arch/arm/dts/imx6ul.dtsi
> @@ -1,19 +1,23 @@
> -/*
> - * Copyright 2015 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright 2015 Freescale Semiconductor, Inc.
>
> #include <dt-bindings/clock/imx6ul-clock.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include "imx6ul-pinfunc.h"
> -#include "skeleton.dtsi"
>
> / {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + /*
> + * The decompressor and also some bootloaders rely on a
> + * pre-existing /chosen node to be available to insert the
> + * command line and merge other ATAGS info.
> + */
> + chosen {};
> +
> aliases {
> ethernet0 = &fec1;
> ethernet1 = &fec2;
> @@ -59,14 +63,17 @@
> device_type = "cpu";
> reg = <0>;
> clock-latency = <61036>; /* two CLK32 periods */
> + #cooling-cells = <2>;
> operating-points = <
> /* kHz uV */
> + 696000 1275000
> 528000 1175000
> 396000 1025000
> 198000 950000
> >;
> fsl,soc-operating-points = <
> /* KHz uV */
> + 696000 1275000
> 528000 1175000
> 396000 1175000
> 198000 1175000
> @@ -77,30 +84,39 @@
> <&clks IMX6UL_CA7_SECONDARY_SEL>,
> <&clks IMX6UL_CLK_STEP>,
> <&clks IMX6UL_CLK_PLL1_SW>,
> - <&clks IMX6UL_CLK_PLL1_SYS>,
> - <&clks IMX6UL_PLL1_BYPASS>,
> - <&clks IMX6UL_CLK_PLL1>,
> - <&clks IMX6UL_PLL1_BYPASS_SRC>,
> - <&clks IMX6UL_CLK_OSC>;
> + <&clks IMX6UL_CLK_PLL1_SYS>;
> clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
> "secondary_sel", "step", "pll1_sw",
> - "pll1_sys", "pll1_bypass", "pll1",
> - "pll1_bypass_src", "osc";
> + "pll1_sys";
> arm-supply = <®_arm>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> - intc: interrupt-controller at 00a01000 {
> - compatible = "arm,cortex-a7-gic";
> + intc: interrupt-controller at a01000 {
> + compatible = "arm,gic-400", "arm,cortex-a7-gic";
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_HIGH)>;
> #interrupt-cells = <3>;
> interrupt-controller;
> + interrupt-parent = <&intc>;
> reg = <0x00a01000 0x1000>,
> - <0x00a02000 0x1000>,
> + <0x00a02000 0x2000>,
> <0x00a04000 0x2000>,
> <0x00a06000 0x2000>;
> };
>
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>;
> + interrupt-parent = <&intc>;
> + status = "disabled";
> + };
> +
> ckil: clock-cli {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -129,6 +145,22 @@
> clock-output-names = "ipp_di1";
> };
>
> + tempmon: tempmon {
> + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
> + interrupt-parent = <&gpc>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
> + nvmem-cell-names = "calib", "temp_grade";
> + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupt-parent = <&gpc>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> soc {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -136,18 +168,12 @@
> interrupt-parent = <&gpc>;
> ranges;
>
> - pmu {
> - compatible = "arm,cortex-a7-pmu";
> - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - };
> -
> - ocram: sram at 00900000 {
> + ocram: sram at 900000 {
> compatible = "mmio-sram";
> reg = <0x00900000 0x20000>;
> };
>
> - dma_apbh: dma-apbh at 01804000 {
> + dma_apbh: dma-apbh at 1804000 {
> compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
> reg = <0x01804000 0x2000>;
> interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
> @@ -160,7 +186,7 @@
> clocks = <&clks IMX6UL_CLK_APBHDMA>;
> };
>
> - gpmi: gpmi-nand at 01806000 {
> + gpmi: gpmi-nand at 1806000 {
> compatible = "fsl,imx6q-gpmi-nand";
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -180,22 +206,21 @@
> status = "disabled";
> };
>
> - aips1: aips-bus at 02000000 {
> + aips1: aips-bus at 2000000 {
> compatible = "fsl,aips-bus", "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x02000000 0x100000>;
> ranges;
>
> - spba-bus at 02000000 {
> + spba-bus at 2000000 {
> compatible = "fsl,spba-bus", "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x02000000 0x40000>;
> ranges;
> - u-boot,dm-spl;
>
> - ecspi1: ecspi at 02008000 {
> + ecspi1: spi at 2008000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
> @@ -207,7 +232,7 @@
> status = "disabled";
> };
>
> - ecspi2: ecspi at 0200c000 {
> + ecspi2: spi at 200c000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
> @@ -219,7 +244,7 @@
> status = "disabled";
> };
>
> - ecspi3: ecspi at 02010000 {
> + ecspi3: spi at 2010000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
> @@ -231,7 +256,7 @@
> status = "disabled";
> };
>
> - ecspi4: ecspi at 02014000 {
> + ecspi4: spi at 2014000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
> @@ -243,7 +268,7 @@
> status = "disabled";
> };
>
> - uart7: serial at 02018000 {
> + uart7: serial at 2018000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x02018000 0x4000>;
> @@ -254,7 +279,7 @@
> status = "disabled";
> };
>
> - uart1: serial at 02020000 {
> + uart1: serial at 2020000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x02020000 0x4000>;
> @@ -265,7 +290,7 @@
> status = "disabled";
> };
>
> - uart8: serial at 02024000 {
> + uart8: serial at 2024000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x02024000 0x4000>;
> @@ -276,7 +301,7 @@
> status = "disabled";
> };
>
> - sai1: sai at 02028000 {
> + sai1: sai at 2028000 {
> #sound-dai-cells = <0>;
> compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
> reg = <0x02028000 0x4000>;
> @@ -291,7 +316,7 @@
> status = "disabled";
> };
>
> - sai2: sai at 0202c000 {
> + sai2: sai at 202c000 {
> #sound-dai-cells = <0>;
> compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
> reg = <0x0202c000 0x4000>;
> @@ -306,7 +331,7 @@
> status = "disabled";
> };
>
> - sai3: sai at 02030000 {
> + sai3: sai at 2030000 {
> #sound-dai-cells = <0>;
> compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
> reg = <0x02030000 0x4000>;
> @@ -322,7 +347,7 @@
> };
> };
>
> - tsc: tsc at 02040000 {
> + tsc: tsc at 2040000 {
> compatible = "fsl,imx6ul-tsc";
> reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
> interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> @@ -333,10 +358,10 @@
> status = "disabled";
> };
>
> - pwm1: pwm at 02080000 {
> + pwm1: pwm at 2080000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x02080000 0x4000>;
> - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_PWM1>,
> <&clks IMX6UL_CLK_PWM1>;
> clock-names = "ipg", "per";
> @@ -344,10 +369,10 @@
> status = "disabled";
> };
>
> - pwm2: pwm at 02084000 {
> + pwm2: pwm at 2084000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x02084000 0x4000>;
> - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_PWM2>,
> <&clks IMX6UL_CLK_PWM2>;
> clock-names = "ipg", "per";
> @@ -355,10 +380,10 @@
> status = "disabled";
> };
>
> - pwm3: pwm at 02088000 {
> + pwm3: pwm at 2088000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x02088000 0x4000>;
> - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_PWM3>,
> <&clks IMX6UL_CLK_PWM3>;
> clock-names = "ipg", "per";
> @@ -366,10 +391,10 @@
> status = "disabled";
> };
>
> - pwm4: pwm at 0208c000 {
> + pwm4: pwm at 208c000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x0208c000 0x4000>;
> - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_PWM4>,
> <&clks IMX6UL_CLK_PWM4>;
> clock-names = "ipg", "per";
> @@ -377,27 +402,29 @@
> status = "disabled";
> };
>
> - can1: flexcan at 02090000 {
> + can1: flexcan at 2090000 {
> compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
> reg = <0x02090000 0x4000>;
> interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
> <&clks IMX6UL_CLK_CAN1_SERIAL>;
> clock-names = "ipg", "per";
> + fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
> status = "disabled";
> };
>
> - can2: flexcan at 02094000 {
> + can2: flexcan at 2094000 {
> compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
> reg = <0x02094000 0x4000>;
> interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
> <&clks IMX6UL_CLK_CAN2_SERIAL>;
> clock-names = "ipg", "per";
> + fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
> status = "disabled";
> };
>
> - gpt1: gpt at 02098000 {
> + gpt1: gpt at 2098000 {
> compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
> reg = <0x02098000 0x4000>;
> interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> @@ -406,11 +433,12 @@
> clock-names = "ipg", "per";
> };
>
> - gpio1: gpio at 0209c000 {
> + gpio1: gpio at 209c000 {
> compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
> reg = <0x0209c000 0x4000>;
> interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_GPIO1>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -419,11 +447,12 @@
> <&iomuxc 16 33 16>;
> };
>
> - gpio2: gpio at 020a0000 {
> + gpio2: gpio at 20a0000 {
> compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
> reg = <0x020a0000 0x4000>;
> interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_GPIO2>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -431,11 +460,12 @@
> gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
> };
>
> - gpio3: gpio at 020a4000 {
> + gpio3: gpio at 20a4000 {
> compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
> reg = <0x020a4000 0x4000>;
> interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_GPIO3>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -443,11 +473,12 @@
> gpio-ranges = <&iomuxc 0 65 29>;
> };
>
> - gpio4: gpio at 020a8000 {
> + gpio4: gpio at 20a8000 {
> compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
> reg = <0x020a8000 0x4000>;
> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_GPIO4>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -455,11 +486,12 @@
> gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
> };
>
> - gpio5: gpio at 020ac000 {
> + gpio5: gpio at 20ac000 {
> compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
> reg = <0x020ac000 0x4000>;
> interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_GPIO5>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -467,9 +499,10 @@
> gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
> };
>
> - fec2: ethernet at 020b4000 {
> + fec2: ethernet at 20b4000 {
> compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
> reg = <0x020b4000 0x4000>;
> + interrupt-names = "int0", "pps";
> interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_ENET>,
> @@ -484,7 +517,7 @@
> status = "disabled";
> };
>
> - kpp: kpp at 020b8000 {
> + kpp: kpp at 20b8000 {
> compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp",
> "fsl,imx21-kpp";
> reg = <0x020b8000 0x4000>;
> interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> @@ -492,14 +525,14 @@
> status = "disabled";
> };
>
> - wdog1: wdog at 020bc000 {
> + wdog1: wdog at 20bc000 {
> compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
> reg = <0x020bc000 0x4000>;
> interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_WDOG1>;
> };
>
> - wdog2: wdog at 020c0000 {
> + wdog2: wdog at 20c0000 {
> compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
> reg = <0x020c0000 0x4000>;
> interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> @@ -507,7 +540,7 @@
> status = "disabled";
> };
>
> - clks: ccm at 020c4000 {
> + clks: ccm at 20c4000 {
> compatible = "fsl,imx6ul-ccm";
> reg = <0x020c4000 0x4000>;
> interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> @@ -517,7 +550,7 @@
> clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
> };
>
> - anatop: anatop at 020c8000 {
> + anatop: anatop at 20c8000 {
> compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
> "syscon", "simple-bus";
> reg = <0x020c8000 0x1000>;
> @@ -574,7 +607,7 @@
> };
> };
>
> - usbphy1: usbphy at 020c9000 {
> + usbphy1: usbphy at 20c9000 {
> compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
> reg = <0x020c9000 0x1000>;
> interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> @@ -583,7 +616,7 @@
> fsl,anatop = <&anatop>;
> };
>
> - usbphy2: usbphy at 020ca000 {
> + usbphy2: usbphy at 20ca000 {
> compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
> reg = <0x020ca000 0x1000>;
> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> @@ -592,7 +625,7 @@
> fsl,anatop = <&anatop>;
> };
>
> - snvs: snvs at 020cc000 {
> + snvs: snvs at 20cc000 {
> compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
> reg = <0x020cc000 0x4000>;
>
> @@ -608,6 +641,7 @@
> compatible = "syscon-poweroff";
> regmap = <&snvs>;
> offset = <0x38>;
> + value = <0x60>;
> mask = <0x60>;
> status = "disabled";
> };
> @@ -619,19 +653,23 @@
> linux,keycode = <KEY_POWER>;
> wakeup-source;
> };
> +
> + snvs_lpgpr: snvs-lpgpr {
> + compatible = "fsl,imx6ul-snvs-lpgpr";
> + };
> };
>
> - epit1: epit at 020d0000 {
> + epit1: epit at 20d0000 {
> reg = <0x020d0000 0x4000>;
> interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - epit2: epit at 020d4000 {
> + epit2: epit at 20d4000 {
> reg = <0x020d4000 0x4000>;
> interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - src: src at 020d8000 {
> + src: src at 20d8000 {
> compatible = "fsl,imx6ul-src", "fsl,imx51-src";
> reg = <0x020d8000 0x4000>;
> interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> @@ -639,7 +677,7 @@
> #reset-cells = <1>;
> };
>
> - gpc: gpc at 020dc000 {
> + gpc: gpc at 20dc000 {
> compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
> reg = <0x020dc000 0x4000>;
> interrupt-controller;
> @@ -648,18 +686,18 @@
> interrupt-parent = <&intc>;
> };
>
> - iomuxc: iomuxc at 020e0000 {
> + iomuxc: iomuxc at 20e0000 {
> compatible = "fsl,imx6ul-iomuxc";
> reg = <0x020e0000 0x4000>;
> };
>
> - gpr: iomuxc-gpr at 020e4000 {
> + gpr: iomuxc-gpr at 20e4000 {
> compatible = "fsl,imx6ul-iomuxc-gpr",
> "fsl,imx6q-iomuxc-gpr", "syscon";
> reg = <0x020e4000 0x4000>;
> };
>
> - gpt2: gpt at 020e8000 {
> + gpt2: gpt at 20e8000 {
> compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
> reg = <0x020e8000 0x4000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> @@ -668,19 +706,19 @@
> clock-names = "ipg", "per";
> };
>
> - sdma: sdma at 020ec000 {
> + sdma: sdma at 20ec000 {
> compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
> "fsl,imx35-sdma";
> reg = <0x020ec000 0x4000>;
> interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clks IMX6UL_CLK_SDMA>,
> + clocks = <&clks IMX6UL_CLK_IPG>,
> <&clks IMX6UL_CLK_SDMA>;
> clock-names = "ipg", "ahb";
> #dma-cells = <3>;
> fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
> };
>
> - pwm5: pwm at 020f0000 {
> + pwm5: pwm at 20f0000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x020f0000 0x4000>;
> interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> @@ -691,7 +729,7 @@
> status = "disabled";
> };
>
> - pwm6: pwm at 020f4000 {
> + pwm6: pwm at 20f4000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x020f4000 0x4000>;
> interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> @@ -702,7 +740,7 @@
> status = "disabled";
> };
>
> - pwm7: pwm at 020f8000 {
> + pwm7: pwm at 20f8000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x020f8000 0x4000>;
> interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> @@ -713,7 +751,7 @@
> status = "disabled";
> };
>
> - pwm8: pwm at 020fc000 {
> + pwm8: pwm at 20fc000 {
> compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
> reg = <0x020fc000 0x4000>;
> interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> @@ -725,14 +763,44 @@
> };
> };
>
> - aips2: aips-bus at 02100000 {
> + aips2: aips-bus at 2100000 {
> compatible = "fsl,aips-bus", "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x02100000 0x100000>;
> ranges;
>
> - usbotg1: usb at 02184000 {
> + crypto: caam at 2140000 {
> + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x2140000 0x3c000>;
> + ranges = <0 0x2140000 0x3c000>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks
> IMX6UL_CLK_CAAM_ACLK>,
> + <&clks IMX6UL_CLK_CAAM_MEM>;
> + clock-names = "ipg", "aclk", "mem";
> +
> + sec_jr0: jr0 at 1000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x1000 0x1000>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr1: jr1 at 2000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x2000 0x1000>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr2: jr2 at 3000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x3000 0x1000>;
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + usbotg1: usb at 2184000 {
> compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
> reg = <0x02184000 0x200>;
> interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> @@ -746,7 +814,7 @@
> status = "disabled";
> };
>
> - usbotg2: usb at 02184200 {
> + usbotg2: usb at 2184200 {
> compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
> reg = <0x02184200 0x200>;
> interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> @@ -759,15 +827,16 @@
> status = "disabled";
> };
>
> - usbmisc: usbmisc at 02184800 {
> + usbmisc: usbmisc at 2184800 {
> #index-cells = <1>;
> compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
> reg = <0x02184800 0x200>;
> };
>
> - fec1: ethernet at 02188000 {
> + fec1: ethernet at 2188000 {
> compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
> reg = <0x02188000 0x4000>;
> + interrupt-names = "int0", "pps";
> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clks IMX6UL_CLK_ENET>,
> @@ -782,7 +851,7 @@
> status = "disabled";
> };
>
> - usdhc1: usdhc at 02190000 {
> + usdhc1: usdhc at 2190000 {
> compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
> reg = <0x02190000 0x4000>;
> interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> @@ -794,7 +863,7 @@
> status = "disabled";
> };
>
> - usdhc2: usdhc at 02194000 {
> + usdhc2: usdhc at 2194000 {
> compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
> reg = <0x02194000 0x4000>;
> interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> @@ -806,7 +875,7 @@
> status = "disabled";
> };
>
> - adc1: adc at 02198000 {
> + adc1: adc at 2198000 {
> compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
> reg = <0x02198000 0x4000>;
> interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> @@ -818,7 +887,7 @@
> status = "disabled";
> };
>
> - i2c1: i2c at 021a0000 {
> + i2c1: i2c at 21a0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
> @@ -828,7 +897,7 @@
> status = "disabled";
> };
>
> - i2c2: i2c at 021a4000 {
> + i2c2: i2c at 21a4000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
> @@ -838,7 +907,7 @@
> status = "disabled";
> };
>
> - i2c3: i2c at 021a8000 {
> + i2c3: i2c at 21a8000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
> @@ -848,12 +917,44 @@
> status = "disabled";
> };
>
> - mmdc: mmdc at 021b0000 {
> + memory-controller at 21b0000 {
> compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
> reg = <0x021b0000 0x4000>;
> + clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
> + };
> +
> + weim: weim at 21b8000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
> + reg = <0x021b8000 0x4000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_EIM>;
> + fsl,weim-cs-gpr = <&gpr>;
> + status = "disabled";
> + };
> +
> + ocotp: ocotp-ctrl at 21bc000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,imx6ul-ocotp", "syscon";
> + reg = <0x021bc000 0x4000>;
> + clocks = <&clks IMX6UL_CLK_OCOTP>;
> +
> + tempmon_calib: calib at 38 {
> + reg = <0x38 4>;
> + };
> +
> + tempmon_temp_grade: temp-grade at 20 {
> + reg = <0x20 4>;
> + };
> +
> + cpu_speed_grade: speed-grade at 10 {
> + reg = <0x10 4>;
> + };
> };
>
> - lcdif: lcdif at 021c8000 {
> + lcdif: lcdif at 21c8000 {
> compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
> reg = <0x021c8000 0x4000>;
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> @@ -864,7 +965,7 @@
> status = "disabled";
> };
>
> - qspi: qspi at 021e0000 {
> + qspi: spi at 21e0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
> @@ -877,7 +978,7 @@
> status = "disabled";
> };
>
> - wdog3: wdog at 021e4000 {
> + wdog3: wdog at 21e4000 {
> compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
> reg = <0x021e4000 0x4000>;
> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> @@ -885,7 +986,7 @@
> status = "disabled";
> };
>
> - uart2: serial at 021e8000 {
> + uart2: serial at 21e8000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x021e8000 0x4000>;
> @@ -896,7 +997,7 @@
> status = "disabled";
> };
>
> - uart3: serial at 021ec000 {
> + uart3: serial at 21ec000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x021ec000 0x4000>;
> @@ -907,7 +1008,7 @@
> status = "disabled";
> };
>
> - uart4: serial at 021f0000 {
> + uart4: serial at 21f0000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x021f0000 0x4000>;
> @@ -918,7 +1019,7 @@
> status = "disabled";
> };
>
> - uart5: serial at 021f4000 {
> + uart5: serial at 21f4000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x021f4000 0x4000>;
> @@ -929,7 +1030,7 @@
> status = "disabled";
> };
>
> - i2c4: i2c at 021f8000 {
> + i2c4: i2c at 21f8000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
> @@ -939,7 +1040,7 @@
> status = "disabled";
> };
>
> - uart6: serial at 021fc000 {
> + uart6: serial at 21fc000 {
> compatible = "fsl,imx6ul-uart",
> "fsl,imx6q-uart";
> reg = <0x021fc000 0x4000>;
> diff --git a/include/dt-bindings/clock/imx6ul-clock.h
> b/include/dt-bindings/clock/imx6ul-clock.h
> index 4623f170a8..79094338e6 100644
> --- a/include/dt-bindings/clock/imx6ul-clock.h
> +++ b/include/dt-bindings/clock/imx6ul-clock.h
> @@ -1,10 +1,6 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> /*
> - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> */
>
> #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
> @@ -105,7 +101,7 @@
> #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
> #define IMX6UL_CLK_ARM 93
> #define IMX6UL_CLK_PERIPH_CLK2 94
> -#define IMX6UL_CLK_PERIPH2_CLK2 95
> +#define IMX6UL_CLK_PERIPH2_CLK2 95
> #define IMX6UL_CLK_AHB 96
> #define IMX6UL_CLK_MMDC_PODF 97
> #define IMX6UL_CLK_AXI_PODF 98
> @@ -235,20 +231,32 @@
> #define IMX6UL_CLK_CSI_PODF 222
> #define IMX6UL_CLK_PLL3_120M 223
> #define IMX6UL_CLK_KPP 224
> -/* For i.MX6ULL */
> -#define IMX6UL_CLK_ESAI_SEL 224
> -#define IMX6UL_CLK_ESAI_PRED 225
> -#define IMX6UL_CLK_ESAI_PODF 226
> -#define IMX6UL_CLK_ESAI_EXTAL 227
> -#define IMX6UL_CLK_ESAI_MEM 228
> -#define IMX6UL_CLK_ESAI_IPG 229
> -#define IMX6UL_CLK_DCP_CLK 230
> -#define IMX6UL_CLK_EPDC_PRE_SEL 231
> -#define IMX6UL_CLK_EPDC_SEL 232
> -#define IMX6UL_CLK_EPDC_PODF 233
> -#define IMX6UL_CLK_EPDC_ACLK 234
> -#define IMX6UL_CLK_EPDC_PIX 235
> +#define IMX6ULL_CLK_ESAI_PRED 225
> +#define IMX6ULL_CLK_ESAI_PODF 226
> +#define IMX6ULL_CLK_ESAI_EXTAL 227
> +#define IMX6ULL_CLK_ESAI_MEM 228
> +#define IMX6ULL_CLK_ESAI_IPG 229
> +#define IMX6ULL_CLK_DCP_CLK 230
> +#define IMX6ULL_CLK_EPDC_PRE_SEL 231
> +#define IMX6ULL_CLK_EPDC_SEL 232
> +#define IMX6ULL_CLK_EPDC_PODF 233
> +#define IMX6ULL_CLK_EPDC_ACLK 234
> +#define IMX6ULL_CLK_EPDC_PIX 235
> +#define IMX6ULL_CLK_ESAI_SEL 236
> +#define IMX6UL_CLK_CKO1_SEL 237
> +#define IMX6UL_CLK_CKO1_PODF 238
> +#define IMX6UL_CLK_CKO1 239
> +#define IMX6UL_CLK_CKO2_SEL 240
> +#define IMX6UL_CLK_CKO2_PODF 241
> +#define IMX6UL_CLK_CKO2 242
> +#define IMX6UL_CLK_CKO 243
> +#define IMX6UL_CLK_GPIO1 244
> +#define IMX6UL_CLK_GPIO2 245
> +#define IMX6UL_CLK_GPIO3 246
> +#define IMX6UL_CLK_GPIO4 247
> +#define IMX6UL_CLK_GPIO5 248
> +#define IMX6UL_CLK_MMDC_P1_IPG 249
>
> -#define IMX6UL_CLK_END 236
> +#define IMX6UL_CLK_END 250
>
> #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
> --
> 2.16.4
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