[U-Boot] [PATCH 7/7] board: atmel: sama5d2_wlsom1_ek: add SPL support
Eugen.Hristev at microchip.com
Eugen.Hristev at microchip.com
Thu Aug 8 07:48:35 UTC 2019
From: Eugen Hristev <eugen.hristev at microchip.com>
Add support for SPL for this board: DRAM initialization, PMC initialization,
MMC boot.
Signed-off-by: Eugen Hristev <eugen.hristev at microchip.com>
---
arch/arm/mach-at91/Kconfig | 1 +
.../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 147 +++++++++++++++++++++
configs/sama5d27_wlsom1_ek_mmc_defconfig | 25 +++-
include/configs/sama5d27_wlsom1_ek.h | 16 ++-
4 files changed, 185 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index ce0b1b4..1434328 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -189,6 +189,7 @@ config TARGET_SAMA5D27_WLSOM1_EK
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
+ select SUPPORT_SPL
help
The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package),
a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index 483ec82..3663ae4 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -78,3 +78,150 @@ int dram_init(void)
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_SD_BOOT
+void spl_mmc_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SD_BOOT
+ spl_mmc_init();
+#endif
+}
+
+void spl_display_print(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_ZQ_SHORT |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
+
+ /*
+ * The AD220032D average time between REFRESH commands (Trefi): 3.9us
+ * 3.9us * 164MHz = 639.6 = 0x27F.
+ */
+ ddrc->rtr = 0x27f;
+ /* Enable Adjust Refresh Rate */
+ ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
+
+ ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+
+ ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
+
+ /*
+ * According to the sama5d2 datasheet and the following values:
+ * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
+ * Warning: note that the values T driftrate and V driftrate are dependent on
+ * the application environment.
+ * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
+ * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
+ * this timer to 0xFFFE.
+ */
+ ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
+
+ /*
+ * MR4 Read interval is dependent on the application environment.
+ * Here, we want to maximize this value as temperature is supposed
+ * to vary slowly in the application chosen.
+ * If Trefi is 3.9us, we have:
+ * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
+ */
+ ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ ddrc_conf(&ddrc_config);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(40) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 6b11fcb..d7329a2 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -2,12 +2,20 @@ CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
-CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
@@ -15,9 +23,13 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DISPLAY_PRINT=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -31,9 +43,15 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
@@ -56,6 +74,7 @@ CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
@@ -64,9 +83,11 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER_HII is not set
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
index cc41560..6bcbc06 100644
--- a/include/configs/sama5d27_wlsom1_ek.h
+++ b/include/configs/sama5d27_wlsom1_ek.h
@@ -19,16 +19,28 @@
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x218000
+#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-/* NAND flash */
-#undef CONFIG_CMD_NAND
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE 0x200000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#endif
--
2.7.4
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