[U-Boot] [PATCH u-boot-marvell 1/1] pci: pci_mvebu: set BAR0 after memory space is set

[Chris Packham]

Hi Marek,

On Thu, Aug 8, 2019 at 1:02 AM Marek Behún <marek.behun at nic.cz> wrote:
>
> The non-DM version of this driver used to set BAR0 register after the
> calls to pci_set_region.
> I found out that for some strange reason the ath10k driver in kernel
> fails to work if this is done the other way around.
> I know that Linux's driver should not depend on how U-Boot does things,
> but for some strange reason it does and this seems to be the simplest
> solution. Fix it since it caused regressions on Omnia.
>
> Signed-off-by: Marek Behún <marek.behun at nic.cz>
> Cc: Stefan Roese <sr at denx.de>
> Cc: Dirk Eibach <dirk.eibach at gdsys.cc>
> Cc: Mario Six <mario.six at gdsys.cc>
> Cc: Chris Packham <chris.packham at alliedtelesis.co.nz>
> Cc: Phil Sutter <phil at nwl.cc>
> Cc: VlaoMao <vlaomao at gmail.com>

Tested-by: Chris Packham <judge.packham at gmail.com>

> ---
>  drivers/pci/pci_mvebu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index e21dc10c2f..f9b08f38a1 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -313,10 +313,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
>         reg |= BIT(10);         /* disable interrupts */
>         writel(reg, pcie->base + PCIE_CMD_OFF);
>
> -       /* Set BAR0 to internal registers */
> -       writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> -       writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
> -
>         /* PCI memory space */
>         pci_set_region(hose->regions + 0, pcie->mem.start,
>                        pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
> @@ -326,6 +322,10 @@ static int mvebu_pcie_probe(struct udevice *dev)
>                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>         hose->region_count = 2;
>
> +       /* Set BAR0 to internal registers */
> +       writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> +       writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
> +
>         bus++;
>
>         return 0;
> --
> 2.21.0
>
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