[U-Boot] Pull request: u-boot-riscv/master

[uboot at andestech.com]

Hi Tom,

Please pull some riscv updates:

- Fix sifive serial y-modem transfer.
- Access CSRs using CSR numbers.
- Update doc sifive-fu540
- Support big endian hosts and target.
- Support SPL and OpenSBI (FW_DYNAMIC firmware) boot.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/570682542

Thanks
Rick


The following changes since commit feb5a02f869d5678190dfc915ef6c2781b4f7a6c:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-08-10 17:57:58 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 30c150bae4e3a61f87a159579cd3784f4d64e79e:

  riscv: qemu: Fix kconfig build warning (2019-08-12 13:30:53 +0800)

----------------------------------------------------------------
Anup Patel (1):
      doc: sifive-fu540: Update README to explicitly load DTB for Linux

Bin Meng (3):
      riscv: Sync csr.h with Linux kernel v5.2
      riscv: Access CSRs using CSR numbers
      riscv: qemu: Fix kconfig build warning

Lukas Auer (10):
      fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL
      Makefile: support building SPL FIT images without device trees
      spl: fit: use U-Boot device tree when FIT image has no device tree
      riscv: add run mode configuration for SPL
      riscv: add SPL support
      riscv: support SPL stack and global data relocation
      riscv: add a generic FIT generator script
      riscv: set default FIT generator script and build target for SPL builds
      riscv: qemu: add SPL configuration
      doc: update QEMU RISC-V documentation

Marcus Comstedt (2):
      riscv: tools: Fix prelink-riscv to work on big endian hosts
      riscv: tools: Add big endian target support to prelink-riscv

Sagar Shrikant Kadam (1):
      riscv : serial: use rx watermark to indicate rx data is present

 Kconfig                                 |   4 +-
 Makefile                                |   8 ++-
 arch/Kconfig                            |   6 ++
 arch/riscv/Kconfig                      |  36 ++++++++--
 arch/riscv/cpu/ax25/Kconfig             |   6 +-
 arch/riscv/cpu/cpu.c                    |  15 ++---
 arch/riscv/cpu/generic/Kconfig          |   5 +-
 arch/riscv/cpu/start.S                  |  65 ++++++++++++++++--
 arch/riscv/cpu/u-boot-spl.lds           |  82 +++++++++++++++++++++++
 arch/riscv/include/asm/asm.h            |  68 +++++++++++++++++++
 arch/riscv/include/asm/csr.h            |  74 ++++++++++++++++-----
 arch/riscv/include/asm/encoding.h       | 240 +-----------------------------------------------------------------
 arch/riscv/include/asm/spl.h            |  31 +++++++++
 arch/riscv/lib/Makefile                 |   8 ++-
 arch/riscv/lib/mkimage_fit_opensbi.sh   | 100 ++++++++++++++++++++++++++++
 arch/riscv/lib/spl.c                    |  48 ++++++++++++++
 board/emulation/qemu-riscv/Kconfig      |  11 ++++
 board/emulation/qemu-riscv/MAINTAINERS  |   2 +
 board/emulation/qemu-riscv/qemu-riscv.c |  17 +++++
 common/spl/spl.c                        |   2 +-
 common/spl/spl_fit.c                    |  37 +++++++----
 configs/qemu-riscv32_spl_defconfig      |  11 ++++
 configs/qemu-riscv64_spl_defconfig      |  12 ++++
 doc/board/emulation/qemu-riscv.rst      |  60 ++++++++++++++++-
 doc/board/sifive/fu540.rst              | 396 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------
 drivers/serial/serial_sifive.c          |  23 ++-----
 include/configs/qemu-riscv.h            |  14 ++++
 include/fdtdec.h                        |   2 +-
 lib/fdtdec.c                            |   6 +-
 tools/prelink-riscv.c                   |  39 ++++++++---
 tools/prelink-riscv.inc                 |  60 +++++++++--------
 31 files changed, 962 insertions(+), 526 deletions(-)
 create mode 100644 arch/riscv/cpu/u-boot-spl.lds
 create mode 100644 arch/riscv/include/asm/asm.h
 create mode 100644 arch/riscv/include/asm/spl.h
 create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh
 create mode 100644 arch/riscv/lib/spl.c
 create mode 100644 configs/qemu-riscv32_spl_defconfig
 create mode 100644 configs/qemu-riscv64_spl_defconfig