[U-Boot] [U-BOOT PATCH 3/3] spi: riscv: use single bit mode for spi transfers

[Sagar Shrikant Kadam]

Use the SPI controller in FU540-C000 soc in one bit mode, rather than using
spi-tx-bus-width and spi-rx-bus-width passed from the device tree.

This patch handles a case where controller mode in format register (0x40)
is configured as per the width specified in the dt-node of the slave
device. For instance if spi-tx-bus-width and spi-rx-bus-width in the flash
device node in dt is set to 4 bit mode, the controller gets configured in
QUAD mode, whereas the spi nor scan tries to read the JEDEC ID with the
reg_proto set to SNOR_PROTO_1_1_1 and fails.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
---
 drivers/spi/spi-sifive.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index 969bd4b..7cf3ea4 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -146,12 +146,7 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi,
 
 	/* Number of wires ? */
 	cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
-	if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
-		cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
-	else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
-		cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
-	else
-		cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+	cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
 
 	/* SPI direction in/out ? */
 	cr &= ~SIFIVE_SPI_FMT_DIR;
-- 
2.7.4