[U-Boot] [PATCH] ARM: DRA7: Fixup DPLL clock rate fixup logic for newer kernels

[Suman Anna]

The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") updates the kernel device-tree blob to adjust
the DSP, IVA and GPU DPLL clocks based on a one-time OPP choice selected
in U-Boot. All these DPLL clocks are children of the cm_core_aon clocks
DT node.

The hierarchy of this clocks DT node has changed in newer Linux kernels
starting from v5.0, and this results in a failure in ft_fixup_clocks()
function to update the clock rates on these newer kernels. Fix this by
updating the lookup logic to look through both the newer and older
DT hierarchy paths for the cm_core_aon clocks node.

Signed-off-by: Suman Anna <s-anna at ti.com>
---
 arch/arm/mach-omap2/omap5/fdt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
index 3626d79199af..8dee555c10c6 100644
--- a/arch/arm/mach-omap2/omap5/fdt.c
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -201,7 +201,9 @@ static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
 	int offs, node_offs, ret, i;
 	uint32_t phandle;
 
-	offs = fdt_path_offset(fdt, "/ocp/l4 at 4a000000/cm_core_aon at 5000/clocks");
+	offs = fdt_path_offset(fdt, "/ocp/interconnect at 4a000000/segment at 0/target-module at 5000/cm_core_aon at 0/clocks");
+	if (offs < 0)
+		offs = fdt_path_offset(fdt, "/ocp/l4 at 4a000000/cm_core_aon at 5000/clocks");
 	if (offs < 0) {
 		debug("Could not find cm_core_aon clocks node path offset : %s\n",
 		      fdt_strerror(offs));
-- 
2.22.0