[U-Boot] Rockpro64_V2.1 2018-07-02 Boot Freeze

[Kurt Miller]

Hi Kever,

On Tue, 2019-08-20 at 10:46 +0800, Kever Yang wrote:
> Hi Kurt,
> 
> 
> Does this patch fix your issue?
> 
> https://patchwork.ozlabs.org/patch/1147457/
> 

Yes! It fixes my boot issue. Thank you for working on it.

However there is a second issue. Only 2G of memory was recognized
instead of the 4G the board has. I added this to get more
debug output:

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 81fc71c051..0f876217c8 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -5,6 +5,10 @@
  * Adapted from coreboot.
  */
 
+#ifndef DEBUG
+#define DEBUG
+#endif
+
 #include <common.h>
 #include <clk.h>
 #include <dm.h>

U-Boot TPL 2019.10-rc2-00036-ga2ca54ff52-dirty (Aug 20 2019 - 09:41:36)
con reg        
cru , cic , grf , sgrf , pmucru , pmu 
Starting SDRAM initialization...
sdram_init: data trained for rank 1, ch 0
sdram_init: data trained for rank 1, ch 1
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
256B stride
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 800 mhz 1, 0
Finish SDRAM initialization...
Trying to boot from BOOTROM
Returning to boot ROM...

Note that both the Row and Size differers from the
rkbin TPL output:

change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride

Regards,
-Kurt