[U-Boot] [PATCH v3 3/8] dm: cache: add v5l2 cache controller driver

[Bin Meng]

Hi Rick,

On Wed, Aug 21, 2019 at 4:16 PM Andes <uboot at andestech.com> wrote:
>
> From: Rick Chen <rick at andestech.com>
>
> Add a v5l2 cache controller driver that is usually found on
> Andes RISC-V ae350 platform. It will parse the cache settings
> from the dtb.
>
> In this version tag and data ram control timing can be adjusted
> by the requirement from the dtb.
>
> Signed-off-by: Rick Chen <rick at andestech.com>
> Cc: KC Lin <kclin at andestech.com>
> ---
>  arch/riscv/include/asm/v5l2cache.h |  58 ++++++++++++++++

This is specific to Andes AX25 SoC, so we should put it into
asm/arch-ax25. Or we completely drop this header file, if this is only
used by the cache-v5l2.c file, and not intended to be used by anyone
else.

>  drivers/cache/Kconfig              |   9 +++
>  drivers/cache/Makefile             |   1 +
>  drivers/cache/cache-v5l2.c         | 139 +++++++++++++++++++++++++++++++++++++
>  4 files changed, 207 insertions(+)
>  create mode 100644 arch/riscv/include/asm/v5l2cache.h
>  create mode 100644 drivers/cache/cache-v5l2.c
>

Regards,
Bin