[U-Boot] [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: 2019年8月26日 13:59
> To: Z.q. Hou <zhiqiang.hou at nxp.com>
> Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>
> Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum
> A003
> 
> Hi Zhiqiang,
> 
> On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou <zhiqiang.hou at nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> >
> > In the workaround of P4080 erratum A003, it uses the macro
> > CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
> register
> > address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as
> > following:
> >
> >         (CONFIG_SYS_IMMR +
> CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
> >
> > The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
> defined
> > on both corenet and non-corenet platforms (though it should be defined
> > only on corenet platforms), but the macro
> > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet
> > platforms, so when enabled this driver on non-corenet platforms,
> 
> so when enabling

The following series will enable DM PCIe on some PowerPC platforms including
MPC8548CDS, which isn't a CORENET platform.
http://patchwork.ozlabs.org/project/uboot/list/?series=120966

> 
> > the following build error will come up:
> >
> 
> This patch still does not look correct to me.
> 
> So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so the
> CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in the
> P4080 codes.

The CONFIG_SYS_FSL_CORENET_SERDES_ADDR is a macro for SerDes registers
Address, it is not dedicated for workarounds, and the SerDes registers address
macro was defined on both CORENET and non-CORENET platforms.

> Replacing the macro name to P4080_SERDES_ADDR does not help anything.

As the macro CONFIG_SYS_IMMR is always defined on CORENET and non-CORENET
platforms, so replacing the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET,
which is only defined on CORENET platforms, with the P4080 SerDes registers
address in constant number can resolve the build error on non-CORENET.

Thanks,
Zhiqiang

> 
> > drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port':
> > ./arch/powerpc/include/asm/immap_85xx.h:3000:21: error:
> > 'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use in this
> > function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'?
> >   (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
> >
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > Fix this build error by replacing it with a new added macro for SerDes
> > address of P4080.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > ---
> > V2:
> >  - Replaced CONFIG_SYS_FSL_CORENET_SERDES_ADDR with the CCSR
> base +
> >    P4080 SerDes offset.
> >  - Reworded the change log slightly.
> >
> >  drivers/pci/pcie_fsl.c | 2 +-
> >  drivers/pci/pcie_fsl.h | 2 ++
> >  2 files changed, 3 insertions(+), 1 deletion(-)
> >
> 
> Regards,
> Bin