[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou <zhiqiang.hou at nxp.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; Wolfgang Denk <wd at denx.de>; Priyanka
> Jain <priyanka.jain at nxp.com>; Shengzhou Liu <shengzhou.liu at nxp.com>
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> 
> On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> wrote:
> >
> > P2020 integrated 3 PCIe controllers, which is compatible with the PCI
> > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > DT node for each PCIe controller.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > ---
> >  arch/powerpc/dts/p2020-post.dtsi     | 30
> ++++++++++++++++++++++++++++++
> >  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
> >  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
> >  3 files changed, 64 insertions(+)
> >
> > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > b/arch/powerpc/dts/p2020-post.dtsi
> > index f20d1fa..f696f35 100644
> > --- a/arch/powerpc/dts/p2020-post.dtsi
> > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > @@ -25,3 +25,33 @@
> >                 last-interrupt-source = <255>;
> >         };
> >  };
> > +
> > +/* PCIe controller base address 0x8000 */
> > +&pci2 {
> 
> pci0?

Describe the controller index and starting address according to P2020 RM.

> 
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <0>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0x9000 */
> > +&pci1 {
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <1>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0xa000 */
> > +&pci0 {
> 
> pci2?
> 
> > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > +       law_trgt_if = <2>;
> > +       #address-cells = <3>;
> > +       #size-cells = <2>;
> > +       device_type = "pci";
> > +       bus-range = <0x0 0xff>;
> > +};
> > diff --git a/arch/powerpc/dts/p2020rdb-pc.dts
> > b/arch/powerpc/dts/p2020rdb-pc.dts
> > index 4800b76..08befd4 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc.dts
> > @@ -18,6 +18,23 @@
> >         soc: soc at ffe00000 {
> >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci2: pcie at ffe08000 {
> > +               reg = <0x0 0xffe08000 0x0 0x1000>;      /* registers
> */
> 
> put <reg> in dtsi?

The same reason as P1020, see #22 of this series.

Thanks,
Zhiqiang

> 
> > +               status = "disabled";
> > +       };
> > +
> > +       pci1: pcie at ffe09000 {
> > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xa0000000 0x0
> 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at ffe0a000 {
> > +               reg = <0x0 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0x0
> 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p2020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > index 8323b90..04b2519 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > @@ -18,6 +18,23 @@
> >         soc: soc at fffe00000 {
> >                 ranges = <0x0 0xf 0xffe00000 0x100000>;
> >         };
> > +
> > +       pci2: pcie at fffe08000 {
> > +               reg = <0xf 0xffe08000 0x0 0x1000>;      /* registers
> */
> > +               status = "disabled";
> > +       };
> > +
> > +       pci1: pcie at fffe09000 {
> > +               reg = <0xf 0xffe09000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0xc0000000 0xc
> 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> > +
> > +       pci0: pcie at fffe0a000 {
> > +               reg = <0xf 0xffe0a000 0x0 0x1000>;      /* registers
> */
> > +               ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000
> 0x0 0x00010000   /* downstream I/O */
> > +                         0x02000000 0x0 0x80000000 0xc
> 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
> > +       };
> >  };
> >
> >  /include/ "p2020-post.dtsi"
> > --
> 
> Regards,
> Bin