[U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes

[Bin Meng]

Hi Zhiqiang,

On Tue, Aug 27, 2019 at 10:46 AM Z.q. Hou <zhiqiang.hou at nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn at gmail.com>
> > Sent: 2019年8月26日 22:50
> > To: Z.q. Hou <zhiqiang.hou at nxp.com>
> > Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Prabhakar Kushwaha
> > <prabhakar.kushwaha at nxp.com>; Wolfgang Denk <wd at denx.de>; Priyanka
> > Jain <priyanka.jain at nxp.com>; Shengzhou Liu <shengzhou.liu at nxp.com>
> > Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> >
> > Hi Zhiqiang,
> >
> > On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > wrote:
> > >
> > > P1020 integrated 2 PCIe controllers, which is compatible with the PCI
> > > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > > DT node for each PCIe controller.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > > ---
> > >  arch/powerpc/dts/p1020-post.dtsi     | 20 ++++++++++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pc.dts     | 12 ++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++
> > >  arch/powerpc/dts/p1020rdb-pd.dts     | 12 ++++++++++++
> > >  4 files changed, 56 insertions(+)
> > >
> > > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > > b/arch/powerpc/dts/p1020-post.dtsi
> > > index e1a4f50..1e5e678 100644
> > > --- a/arch/powerpc/dts/p1020-post.dtsi
> > > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > > @@ -25,3 +25,23 @@
> > >                 last-interrupt-source = <255>;
> > >         };
> > >  };
> > > +
> > > +/* PCIe controller base address 0x9000 */
> > > +&pci1 {
> > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > +       law_trgt_if = <1>;
> > > +       #address-cells = <3>;
> > > +       #size-cells = <2>;
> > > +       device_type = "pci";
> > > +       bus-range = <0x0 0xff>;
> > > +};
> > > +
> > > +/* PCIe controller base address 0xa000 */
> > > +&pci0 {
> > > +       compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > +       law_trgt_if = <2>;
> > > +       #address-cells = <3>;
> > > +       #size-cells = <2>;
> > > +       device_type = "pci";
> > > +       bus-range = <0x0 0xff>;
> > > +};
> > > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > > b/arch/powerpc/dts/p1020rdb-pc.dts
> > > index fd68b8b..7ebaa61 100644
> > > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > > @@ -18,6 +18,18 @@
> > >         soc: soc at ffe00000 {
> > >                 ranges = <0x0 0x0 0xffe00000 0x100000>;
> > >         };
> > > +
> > > +       pci1: pcie at ffe09000 {
> >
> > Why this is named as pci1?
>
> The P1020 reference manual said the first controller registers offset begin at 0xa000
> and the second begin at 0x9000.
>
> >
> > > +               reg = <0x0 0xffe09000 0x0 0x1000>;      /* registers
> > */
> >
> > Shouldn't the <reg> property be put in the dtsi file?
>
> The registers starting addresses are different between 32bit and 36bit dts.
>

I see. But looks they are inconsistent. Some of the platforms put the
reg in the dtsi, and some do not. I believe it's because some
platforms force to select CONFIG_PHYS_64BIT hence no need to have two
version of <reg> in DT?

Regards,
Bin