[U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes

[Z.q. Hou]

Hi Bin,

> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: 2019年8月27日 10:56
> To: Z.q. Hou <zhiqiang.hou at nxp.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; Wolfgang Denk <wd at denx.de>; Priyanka
> Jain <priyanka.jain at nxp.com>; Shengzhou Liu <shengzhou.liu at nxp.com>
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> 
> Hi Zhiqiang,
> 
> On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou <zhiqiang.hou at nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn at gmail.com>
> > > Sent: 2019年8月26日 22:50
> > > To: Z.q. Hou <zhiqiang.hou at nxp.com>
> > > Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Prabhakar Kushwaha
> > > <prabhakar.kushwaha at nxp.com>; Wolfgang Denk <wd at denx.de>;
> Priyanka
> > > Jain <priyanka.jain at nxp.com>; Shengzhou Liu
> <shengzhou.liu at nxp.com>
> > > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> > >
> > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > > wrote:
> > > >
> > > > P2020 integrated 3 PCIe controllers, which is compatible with the
> > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is
> > > > to add DT node for each PCIe controller.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > > > ---
> > > >  arch/powerpc/dts/p2020-post.dtsi     | 30
> > > ++++++++++++++++++++++++++++++
> > > >  arch/powerpc/dts/p2020rdb-pc.dts     | 17 +++++++++++++++++
> > > >  arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++++++++++++++
> > > >  3 files changed, 64 insertions(+)
> > > >
> > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > > > b/arch/powerpc/dts/p2020-post.dtsi
> > > > index f20d1fa..f696f35 100644
> > > > --- a/arch/powerpc/dts/p2020-post.dtsi
> > > > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > > > @@ -25,3 +25,33 @@
> > > >                 last-interrupt-source = <255>;
> > > >         };
> > > >  };
> > > > +
> > > > +/* PCIe controller base address 0x8000 */
> > > > +&pci2 {
> > >
> > > pci0?
> >
> > Describe the controller index and starting address according to P2020 RM.
> 
> OK, so will this weird index number (2, 1, 0) break the index calculation log in
> the following patch?

No, the code handled this.

Thanks,
Zhiqiang

> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F1152811%2F&data=02%7C01%7Czhiqian
> g.hou%40nxp.com%7Cb20f64bf19f445e50ce108d72a9a160a%7C686ea1d3b
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C637024713598549064&sdat
> a=WG5PXoeY0zriaxdITqzOJ%2BnT65uzrQ%2FUtwi4JuykXnA%3D&reser
> ved=0
> 
> Regards,
> Bin