[U-Boot] [PATCH v2 01/16] arm: K3: j721e: Add basic support for J721E SoC definition
Lokesh Vutla
lokeshvutla at ti.com
Fri Jun 7 14:01:40 UTC 2019
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
arch/arm/mach-k3/Kconfig | 12 ++++++++++--
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am6_init.c | 6 ------
arch/arm/mach-k3/common.c | 6 ++++++
arch/arm/mach-k3/j721e_init.c | 34 ++++++++++++++++++++++++++++++++++
5 files changed, 51 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/mach-k3/j721e_init.c
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index f25f822205..bf90d49b47 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -7,6 +7,9 @@ choice
config SOC_K3_AM6
bool "TI's K3 based AM6 SoC Family Support"
+config SOC_K3_J721E
+ bool "TI's K3 based J721E SoC Family Support"
+
endchoice
config SYS_SOC
@@ -14,7 +17,8 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
- default 0x80000
+ default 0x80000 if SOC_K3_AM6
+ default 0x100000 if SOC_K3_J721E
help
Describes the total size of the MCU MSRAM. This doesn't
specify the total size of SPL as ROM can use some part
@@ -23,7 +27,8 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
- default 0x58000
+ default 0x58000 if SOC_K3_AM6
+ default 0xc0000 if SOC_K3_J721E
help
Describes the maximum size of the image that ROM can download
from any boot media.
@@ -31,18 +36,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
+ default 0x40280000 if SOC_K3_J721E
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
+ default 0x200 if SOC_K3_J721E
help
Describes the size of MCU Scratchpad RAM.
config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
+ default 0x41cffc00 if SOC_K3_J721E
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 3af7f2ec96..028015ed66 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,6 +4,7 @@
# Lokesh Vutla <lokeshvutla at ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 31fa1c8803..6558fe0ef4 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -210,12 +210,6 @@ u32 spl_boot_device(void)
}
#endif
-#ifndef CONFIG_SYSRESET
-void reset_cpu(ulong ignored)
-{
-}
-#endif
-
#ifdef CONFIG_SYS_K3_SPL_ATF
#define AM6_DEV_MCU_RTI0 134
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 4e7fe2076c..bab5ffdf40 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -138,3 +138,9 @@ int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
return 0;
}
#endif
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(ulong ignored)
+{
+}
+#endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
new file mode 100644
index 0000000000..14b4881527
--- /dev/null
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E: SoC specific initialization
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla at ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+#include "common.h"
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /*
+ * ToDo:
+ * - Store boot rom index.
+ * - unlock mmr.
+ */
+
+#ifdef CONFIG_CPU_V7R
+ setup_k3_mpu_regions();
+#endif
+
+ /* Init DM early */
+ spl_early_init();
+
+ /* Prepare console output */
+ preloader_console_init();
+}
+#endif
--
2.21.0
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