[U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache

[Auer, Lukas]

Hi Rick,

On Wed, 2019-06-05 at 17:39 +0800, Bin Meng wrote:
> Hi Rick,
> 
> On Wed, Jun 5, 2019 at 5:38 PM Rick Chen <rickchen36 at gmail.com> wrote:
> > Hi Bin
> > 
> > > Hi Rick,
> > > 
> > > On Tue, May 28, 2019 at 5:45 PM Andes <uboot at andestech.com> wrote:
> > > > From: Rick Chen <rick at andestech.com>
> > > > 
> > > > Use CCTL command to do d-cache write back and invalidate
> > > > instead of fence.
> > > > 
> > > > Signed-off-by: Rick Chen <rick at andestech.com>
> > > > Cc: Greentime Hu <greentime at andestech.com>
> > > > ---
> > > >  arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++---------
> > > >  1 file changed, 13 insertions(+), 9 deletions(-)
> > > > 
> > > > diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> > > > index 228fc55..d30071e 100644
> > > > --- a/arch/riscv/cpu/ax25/cache.c
> > > > +++ b/arch/riscv/cpu/ax25/cache.c
> > > > @@ -5,17 +5,21 @@
> > > >   */
> > > > 
> > > >  #include <common.h>
> > > > +#include <asm/csr.h>
> > > > +
> > > > +#ifdef CONFIG_RISCV_NDS_CACHE
> > > > +/* mcctlcommand */
> > > > +#define CCTL_REG_MCCTLCOMMAND_NUM      0x7cc
> > > > +
> > > > +/* D-cache operation */
> > > > +#define CCTL_L1D_WBINVAL_ALL   6
> > > > +#endif
> > > > 
> > > >  void flush_dcache_all(void)
> > > >  {
> > > > -       /*
> > > > -        * Andes' AX25 does not have a coherence agent. U-Boot must use data
> > > > -        * cache flush and invalidate functions to keep data in the system
> > > > -        * coherent.
> > > > -        * The implementation of the fence instruction in the AX25 flushes the
> > > > -        * data cache and is used for this purpose.
> > > > -        */
> > > > -       asm volatile ("fence" ::: "memory");
> > > > +#ifdef CONFIG_RISCV_NDS_CACHE
> > > > +       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
> > > 
> > > I think CCTL_REG_MCCTLCOMMAND_NUM is a vendor specific CSR. Does
> > > upstream GCC support this CSR?
> > 
> > Yes. It is a vendor specific CSR. Upstream GCC shall not support it.
> > So I isolate it by CONFIG_RISCV_NDS_CACHE.
> > 
> 
> OK, but I suspect you will need do something for the travis build
> since upstream gcc is used?
> 

How about using the CSR address instead of the name? This way the board
can be built in Travis.

Thanks,
Lukas