[U-Boot] [PATCH v5 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver

[Tudor.Ambarus at microchip.com]

From: Tudor Ambarus <tudor.ambarus at microchip.com>

Describe the DT bindings for the driver of the Atmel QSPI
controller. Taken form linux v5.1-rc5.

Signed-off-by: Tudor Ambarus <tudor.ambarus at microchip.com>
---
v5: no change
v4: no change
v3: no change
v2: no change

 doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt

diff --git a/doc/device-tree-bindings/spi/atmel-quadspi.txt b/doc/device-tree-bindings/spi/atmel-quadspi.txt
new file mode 100644
index 000000000000..7c40ea694352
--- /dev/null
+++ b/doc/device-tree-bindings/spi/atmel-quadspi.txt
@@ -0,0 +1,37 @@
+* Atmel Quad Serial Peripheral Interface (QSPI)
+
+Required properties:
+- compatible:     Should be one of the following:
+		  - "atmel,sama5d2-qspi"
+		  - "microchip,sam9x60-qspi"
+- reg:            Should contain the locations and lengths of the base registers
+                  and the mapped memory.
+- reg-names:      Should contain the resource reg names:
+                  - qspi_base: configuration register address space
+                  - qspi_mmap: memory mapped address space
+- interrupts:     Should contain the interrupt for the device.
+- clocks:         Should reference the peripheral clock and the QSPI system
+                  clock if available.
+- clock-names:    Should contain "pclk" for the peripheral clock and "qspick"
+                  for the system clock when available.
+- #address-cells: Should be <1>.
+- #size-cells:    Should be <0>.
+
+Example:
+
+spi at f0020000 {
+	compatible = "atmel,sama5d2-qspi";
+	reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
+	reg-names = "qspi_base", "qspi_mmap";
+	interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+	clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
+	clock-names = "pclk";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi0_default>;
+
+	m25p80 at 0 {
+		...
+	};
+};
-- 
2.9.5