[U-Boot] [PATCH 0/5] Virtex2 FPGA enhancements

Michal Simek michal.simek at xilinx.com
Wed Jun 19 12:10:16 UTC 2019


On 18. 06. 19 17:47, Robert Hancock wrote:
> These changes add support for slave serial mode, in addition to the
> existing slave SelectMAP mode, for programming Xilinx Virtex2 (and later)
> FPGAs, as well as fixing up code style and an issue with the programming
> sequence.
> 
> Robert Hancock (5):
>   fpga: virtex2: cosmetic: Cleanup code style
>   fpga: virtex2: added Kconfig option
>   fpga: virtex2: Split out image writing from pre/post operations
>   fpga: virtex2: Add additional clock cycles after DONE assertion
>   fpga: virtex2: Add slave serial programming support
> 
>  drivers/fpga/Kconfig   |   8 +
>  drivers/fpga/virtex2.c | 503 +++++++++++++++++++++++++++++--------------------
>  include/virtex2.h      |  13 +-
>  3 files changed, 313 insertions(+), 211 deletions(-)
> 

I have not a problem with this code but my question is what's your plan
about it? Right now none is really calling/building this code.
Are you going to push any platform which will enable this driver?

Thanks,
Michal


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