[U-Boot] imx6: [PATCH] Add support for new board "eval1a"

Lukasz Majewski lukma at denx.de
Wed Jun 19 14:55:46 UTC 2019 

Hi Claudio,

> Hi Lukasz
> 
> Thank you for your answer and your warm welcome. 
> 
> Actually I have tried to enable dm_mmc by including
> 
> select DM
> select DM_MMC
> select OF_CONTROL
> imply CMD_DM

With DM_MMC you also need to enable CONFIG_BLK

Moreover, I don't know how experienced are you with the DM/DTS (the dm
tree command from u-boot prompt), but I would recommend starting with
converting subsystem, which is not used to boot the device (for example
PMIC, I2C, REGULATOR, etc).

In that way you would have a grasp of how things are going and avoid
frustration with bricking the board.

> 
> into kconfig. 
> 
> Unfortunately, this breaks everything. 
> I don’t even get any output on my console. 
> u-boot breaks at 
> in bootstage_error (id=BOOTSTAGE_ID_NEED_RESET) at
> include/bootstage.h:381
> 
> Do you have any links, where I can find further information about how
> to implement device model? I have looked into your provided links.
> Unfortunately i don't see big differences at the moment. 
> 
> I would really like to get the code up to date and in line with the
> latest requirements 😊
> 
> Thanks for your support. 
> Regards
> Claudio
> -----Ursprüngliche Nachricht-----
> Von: Lukasz Majewski <lukma at denx.de> 
> Gesendet: Mittwoch, 19. Juni 2019 10:00
> An: claudio at databyte.ch
> Cc: u-boot at lists.denx.de
> Betreff: Re: [U-Boot] imx6: [PATCH] Add support for new board "eval1a"
> 
> Hi Claudio,
> 
> > Hi Lukasz
> > 
> > Thank you for your answer. 
> > You are right. 
> > I will update my code and send a new patch to the mailing list.  
> 
> In U-Boot now the update to driver model and device tree is now
> ongoing.
> 
> You may want look for some already converted i.MX6 boards as a
> reference (they are not yet in the mainline, but shall be):
> 
> http://patchwork.ozlabs.org/cover/1112747/
> http://patchwork.ozlabs.org/cover/1102875/
> 
> or this series:
> https://patchwork.ozlabs.org/patch/1095619/
> 
> > 
> > Sorry for the inconvenience. This is my first patch to such a big 
> > project.  
> 
> No, You shouldn't be sorry or feel any inconvenience. This is the
> role of the community to help you to get your board into the mainline.
> 
> Please do not afraid to ask. :-)
> 
> > 
> > Regards
> > Claudio
> > 
> > -----Ursprüngliche Nachricht-----
> > Von: Lukasz Majewski <lukma at denx.de>
> > Gesendet: Montag, 17. Juni 2019 11:00
> > An: claudio at databyte.ch
> > Cc: u-boot at lists.denx.de
> > Betreff: Re: [U-Boot] imx6: [PATCH] Add support for new board
> > "eval1a"
> > 
> > Hi Claudio,
> >   
> > > This patch adds support for the latest evalboard Eval 1A from 
> > > databyte  
> > 
> > Please be aware that this board uses the "old" approach, which is
> > not using driver model and device tree description.
> > 
> > The SPL is not (yet) required to be converted to DM/DTS. The U-Boot 
> > proper (u-boot.img) shall use DM/DTS.
> >   
> > > 
> > > Signed-off-by: Claudio Hediger <claudio at databyte.ch>
> > > Cc: Stefano Babic <sbabic at denx.de>
> > > ---
> > > From ecfc11f5507e2a1db2c8981b193017e1fd74f7eb Mon Sep 17 00:00:00
> > > 2001 From: Claudio Hediger <claudio at databyte.ch>
> > > Date: Sun, 9 Jun 2019 15:56:29 +0200
> > > Subject: [PATCH 1/3] Added new file. Not finished yet. Commit
> > > before eclipse
> > > 
> > > ---
> > >  arch/arm/dts/eval1a.dts               | 204
> > > +++++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig         |
> > > 6 + board/databyte.ch/eval1a/Kconfig      |  12 ++
> > >  board/databyte.ch/eval1a/MAINTAINERS  |   7 +
> > >  board/databyte.ch/eval1a/Makefile     |   4 +
> > >  board/databyte.ch/eval1a/eval1a.c     | 211
> > > ++++++++++++++++++++++++++ board/databyte.ch/eval1a/imximage.cfg |
> > > 133 ++++++++++++++++ board/databyte.ch/eval1a/plugin.S     | 173
> > > +++++++++++++++++++++ configs/eval1a_defconfig              |  36
> > > +++++ include/configs/eval1a.h              |  54 +++++++
> > >  10 files changed, 840 insertions(+)  create mode 100644 
> > > arch/arm/dts/eval1a.dts  create mode 100644 
> > > board/databyte.ch/eval1a/Kconfig  create mode 100644 
> > > board/databyte.ch/eval1a/MAINTAINERS
> > >  create mode 100644 board/databyte.ch/eval1a/Makefile  create mode
> > > 100644 board/databyte.ch/eval1a/eval1a.c  create mode 100644 
> > > board/databyte.ch/eval1a/imximage.cfg
> > >  create mode 100644 board/databyte.ch/eval1a/plugin.S  create mode
> > > 100644 configs/eval1a_defconfig  create mode 100644 
> > > include/configs/eval1a.h
> > > 
> > > diff --git a/arch/arm/dts/eval1a.dts b/arch/arm/dts/eval1a.dts
> > > new file mode 100644 index 0000000000..1869abab6a
> > > --- /dev/null
> > > +++ b/arch/arm/dts/eval1a.dts
> > > @@ -0,0 +1,204 @@
> > > +/*
> > > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > modify
> > > + * it under the terms of the GNU General Public License version 2
> > > as
> > > + * published by the Free Software Foundation.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +    
> > 
> > If you port code from linux kernel, then please provide SHA1 ID of
> > the exact commit of copied file.
> >   
> > > +#include "imx6ull.dtsi"
> > > +
> > > +/ {
> > > +	model = "Databyte imx6 Evalboard 1A";
> > > +	compatible = "dtb,eval1a", "fsl,imx6ull";
> > > +
> > > +	chosen {
> > > +		stdout-path = &uart1;
> > > +	};
> > > +
> > > +	memory {
> > > +		reg = <0x80000000 0x20000000>;
> > > +	};
> > > +
> > > +	regulators {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		reg_can_3v3: regulator at 0 {
> > > +			compatible = "regulator-fixed";
> > > +			reg = <0>;
> > > +			regulator-name = "can-3v3";
> > > +			regulator-min-microvolt = <3300000>;
> > > +			regulator-max-microvolt = <3300000>;
> > > +			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
> > > +		};
> > > +
> > > +		reg_sd1_vmmc: regulator at 1 {
> > > +			compatible = "regulator-fixed";
> > > +			regulator-name = "VSD_3V3";
> > > +			regulator-min-microvolt = <3300000>;
> > > +			regulator-max-microvolt = <3300000>;
> > > +			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
> > > +			enable-active-high;
> > > +		};
> > > +
> > > +	};
> > > +
> > > +};
> > > +
> > > +&cpu0 {
> > > +	arm-supply = <&reg_arm>;
> > > +	soc-supply = <&reg_soc>;
> > > +	/*dc-supply = <&reg_gpio_dvfs>;*/
> > > +};
> > > +
> > > +&clks {
> > > +	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
> > > +	assigned-clock-rates = <786432000>; };
> > > +
> > > +&fec1 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_enet1>;
> > > +	phy-mode = "rmii";
> > > +	phy-handle = <&ethphy0>;
> > > +	status = "okay";
> > > +};
> > > +
> > > +&fec2 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_enet2>;
> > > +	phy-mode = "rmii";
> > > +	phy-handle = <&ethphy1>;
> > > +	status = "okay";
> > > +
> > > +	mdio {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		ethphy0: ethernet-phy at 2 {
> > > +			compatible = "micrel,ksz8081";
> > > +			reg = <2>;
> > > +		};
> > > +
> > > +		ethphy1: ethernet-phy at 1 {
> > > +			compatible = "micrel,ksz8081";
> > > +			reg = <1>;
> > > +		};
> > > +	};
> > > +};
> > > +
> > > +
> > > +&iomuxc {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_hog_1>;
> > > +	eval1a {
> > > +
> > > +		pinctrl_enet1: enet1grp {
> > > +			fsl,pins = <
> > > +
> > > MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
> > > +			>;
> > > +		};
> > > +
> > > +		pinctrl_enet2: enet2grp {
> > > +			fsl,pins = <
> > > +				MX6UL_PAD_GPIO1_IO07__ENET2_MDC
> > > 0x1b0b0
> > > +				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO
> > > 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> > > +
> > > MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
> > > +			>;
> > > +		};
> > > +
> > > +		
> > > +		pinctrl_uart1: uart1grp {
> > > +			fsl,pins = <
> > > +
> > > MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> > > +
> > > MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> > > +			>;
> > > +		};
> > > +
> > > +		pinctrl_uart2: uart2grp {
> > > +			fsl,pins = <
> > > +
> > > MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
> > > +
> > > MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
> > > +
> > > MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
> > > +
> > > MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
> > > +			>;
> > > +		};
> > > +
> > > +		pinctrl_uart2dte: uart2dtegrp {
> > > +			fsl,pins = <
> > > +
> > > MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
> > > +
> > > MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
> > > +
> > > MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
> > > +
> > > MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
> > > +			>;
> > > +		};
> > > +
> > > +		pinctrl_usdhc1: usdhc1grp {
> > > +			fsl,pins = <
> > > +				MX6UL_PAD_SD1_CMD__USDHC1_CMD
> > > 0x17059
> > > +				MX6UL_PAD_SD1_CLK__USDHC1_CLK
> > > 0x10071
> > > +				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0
> > > 0x17059
> > > +				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1
> > > 0x17059
> > > +				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2
> > > 0x17059
> > > +				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3
> > > 0x17059
> > > +			>;
> > > +		};
> > > +
> > > +		pinctrl_wdog: wdoggrp {
> > > +			fsl,pins = <
> > > +
> > > MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
> > > +			>;
> > > +		};
> > > +	};
> > > +};
> > > +
> > > +
> > > +&uart1 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_uart1>;
> > > +	status = "okay";
> > > +};
> > > +
> > > +&uart2 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_uart2>;
> > > +	fsl,uart-has-rtscts;
> > > +	/* for DTE mode, add below change */
> > > +	/* fsl,dte-mode; */
> > > +	/* pinctrl-0 = <&pinctrl_uart2dte>; */
> > > +	status = "okay";
> > > +};
> > > +
> > > +&usdhc1 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_usdhc1>;
> > > +	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> > > +	keep-power-in-suspend;
> > > +	enable-sdio-wakeup;
> > > +	vmmc-supply = <&reg_sd1_vmmc>;
> > > +	status = "okay";
> > > +};
> > > +
> > > +&wdog1 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&pinctrl_wdog>;
> > > +	fsl,wdog_b;
> > > +};
> > > diff --git a/arch/arm/mach-imx/mx6/Kconfig 
> > > b/arch/arm/mach-imx/mx6/Kconfig index f513c4c06f..c101be4f18
> > > 100644 --- a/arch/arm/mach-imx/mx6/Kconfig
> > > +++ b/arch/arm/mach-imx/mx6/Kconfig
> > > @@ -196,6 +196,11 @@ config TARGET_EMBESTMX6BOARDS
> > >  	select BOARD_LATE_INIT
> > >  	select SUPPORT_SPL
> > >  
> > > +config TARGET_EVAL1A
> > > +	bool "Databyte eval1a"
> > > +	select BOARD_LATE_INIT
> > > +	select MX6ULL
> > > +
> > >  config TARGET_GE_BX50V3
> > >  	bool "General Electric Bx50v3"
> > >  	select BOARD_LATE_INIT
> > > @@ -559,6 +564,7 @@ source "board/bticino/mamoj/Kconfig"
> > >  source "board/ccv/xpress/Kconfig"
> > >  source "board/compulab/cm_fx6/Kconfig"
> > >  source "board/congatec/cgtqmx6eval/Kconfig"
> > > +source "board/databyte.ch/eval1a/Kconfig"
> > >  source "board/dhelectronics/dh_imx6/Kconfig"
> > >  source "board/el/el6x/Kconfig"
> > >  source "board/embest/mx6boards/Kconfig"
> > > diff --git a/board/databyte.ch/eval1a/Kconfig
> > > b/board/databyte.ch/eval1a/Kconfig
> > > new file mode 100644
> > > index 0000000000..b9b12c4b21
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/Kconfig
> > > @@ -0,0 +1,12 @@
> > > +if TARGET_EVAL1A
> > > +
> > > +config SYS_BOARD
> > > +	default "eval1a"
> > > +
> > > +config SYS_VENDOR
> > > +	default "databyte.ch"
> > > +
> > > +config SYS_CONFIG_NAME
> > > +	default "eval1a"
> > > +
> > > +endif
> > > diff --git a/board/databyte.ch/eval1a/MAINTAINERS
> > > b/board/databyte.ch/eval1a/MAINTAINERS
> > > new file mode 100644
> > > index 0000000000..101cbe5660
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/MAINTAINERS
> > > @@ -0,0 +1,7 @@
> > > +EVAL1A BOARD
> > > +M:	C. Hediger <info at databyte.ch>
> > > +S:	Maintained
> > > +F:	board/databyte.ch/eval1a/
> > > +F:	include/configs/mx6ullevk.h
> > > +F:	configs/mx6ull_14x14_evk_defconfig
> > > +F:	configs/mx6ull_14x14_evk_plugin_defconfig
> > > diff --git a/board/databyte.ch/eval1a/Makefile
> > > b/board/databyte.ch/eval1a/Makefile
> > > new file mode 100644
> > > index 0000000000..4575eb00b7
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/Makefile
> > > @@ -0,0 +1,4 @@
> > > +# SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2016
> > > Freescale +Semiconductor, Inc.
> > > +
> > > +obj-y  := eval1a.o
> > > diff --git a/board/databyte.ch/eval1a/eval1a.c
> > > b/board/databyte.ch/eval1a/eval1a.c
> > > new file mode 100644
> > > index 0000000000..6cb76dce7a
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/eval1a.c
> > > @@ -0,0 +1,211 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > + */
> > > +
> > > +#include <asm/arch/clock.h>
> > > +#include <asm/arch/iomux.h>
> > > +#include <asm/arch/imx-regs.h>
> > > +#include <asm/arch/crm_regs.h>
> > > +#include <asm/arch/mx6-pins.h>
> > > +#include <asm/arch/sys_proto.h>
> > > +#include <asm/gpio.h>
> > > +#include <asm/mach-imx/iomux-v3.h>
> > > +#include <asm/mach-imx/boot_mode.h> #include <asm/io.h> #include 
> > > +<common.h> #include <fsl_esdhc.h> #include <linux/sizes.h>
> > > #include +<mmc.h>
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |
> > > \
> > > +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |
> > > \
> > > +	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> > > +
> > > +#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP
> > > |			\
> > > +	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm
> > > |			\
> > > +	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> > > +
> > > +#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
> > > +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
> > > +	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
> > > +
> > > +#define ETH_PHY_POWER	IMX_GPIO_NR(4, 10)
> > > +    
> > 
> > This is not needed if  you use pinctrl and dts.
> >   
> > > +int dram_init(void)
> > > +{
> > > +	gd->ram_size = imx_ddr_size();
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static iomux_v3_cfg_t const uart1_pads[] = {
> > > +	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX |
> > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > +	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX |
> > > MUX_PAD_CTRL(UART_PAD_CTRL), +};
> > > +
> > > +static iomux_v3_cfg_t const usdhc1_pads[] = {
> > > +	/* 4 bit SD */
> > > +	MX6_PAD_SD1_CLK__USDHC1_CLK |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +	MX6_PAD_SD1_CMD__USDHC1_CMD |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +	MX6_PAD_SD1_DATA0__USDHC1_DATA0 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +	MX6_PAD_SD1_DATA1__USDHC1_DATA1 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +	MX6_PAD_SD1_DATA2__USDHC1_DATA2 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > > +	MX6_PAD_SD1_DATA3__USDHC1_DATA3 |
> > > MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
> > > +
> > > +
> > > +static iomux_v3_cfg_t const fec_pads[] = {
> > > +	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL),
> > > +	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
> > > MUX_PAD_CTRL(ENET_PAD_CTRL), +};
> > > +    
> > 
> > The same here.
> >   
> > > +
> > > +static void setup_iomux_uart(void)
> > > +{
> > > +	imx_iomux_v3_setup_multiple_pads(uart1_pads,
> > > ARRAY_SIZE(uart1_pads));
> > > +}
> > > +
> > > +static void setup_iomux_fec(void)
> > > +{
> > > +	imx_iomux_v3_setup_multiple_pads(fec_pads,
> > > ARRAY_SIZE(fec_pads)); +
> > > +	/* Reset KSZ8041 PHY */
> > > +	gpio_request(ETH_PHY_POWER, "eth_pwr");
> > > +	gpio_direction_output(ETH_PHY_POWER , 1);
> > > +	udelay(15000);
> > > +}
> > > +
> > > +/*
> > > + * Initializes on-chip ethernet controllers.
> > > + * to override, implement board_eth_init()  */ #if
> > > +defined(CONFIG_FEC_MXC) //extern int fecmxc_initialize(bd_t
> > > *bis); +#endif
> > > +
> > > +/*
> > > +int fecmxc_initialize(bd_t *bis)
> > > +{
> > > +	return 0;
> > > +} */
> > > +
> > > +int board_mmc_get_env_dev(int devno) {
> > > +	return devno;
> > > +}
> > > +
> > > +int mmc_map_to_kernel_blk(int devno) {
> > > +	return devno;
> > > +}
> > > +
> > > +int board_early_init_f(void)
> > > +{
> > > +	setup_iomux_uart();
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_FEC_MXC
> > > +int board_eth_init(bd_t *bis)
> > > +{
> > > +	setup_iomux_fec();
> > > +    
> > 
> > fec driver is also converted to DM/DTS.
> >   
> > > +	return 0; //cpu_eth_init(bis);
> > > +}
> > > +
> > > +static int setup_fec(void)
> > > +{
> > > +	struct iomuxc *iomuxc_regs = (struct iomuxc
> > > *)IOMUXC_BASE_ADDR; +
> > > +	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
> > > +	clrsetbits_le32(&iomuxc_regs->gpr[1],
> > > IOMUX_GPR1_FEC_MASK, 0); +
> > > +	return enable_fec_anatop_clock(0, ENET_50MHZ); } #endif
> > > +
> > > +int board_init(void)
> > > +{
> > > +	/* Address of boot parameters */
> > > +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> > > +
> > > +#ifdef	CONFIG_FEC_MXC
> > > +	setup_fec();
> > > +#endif
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +#ifdef CONFIG_CMD_BMODE
> > > +static const struct boot_mode board_boot_modes[] = {
> > > +	/* 4 bit bus width */
> > > +	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
> > > +	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> > > +	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
> > > +	{NULL,	 0},
> > > +};
> > > +#endif
> > > +
> > > +int board_late_init(void)
> > > +{
> > > +#ifdef CONFIG_CMD_BMODE
> > > +	add_board_boot_modes(board_boot_modes);
> > > +#endif
> > > +
> > > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > > +	env_set("board_name", "EVAL");
> > > +	env_set("board_rev", "1A");
> > > +#endif
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +int board_mmc_getcd(struct mmc *mmc) {
> > > +	//Since we cant detect the insertion of an SD-Card, we
> > > always assume that there is one inserted!
> > > +	return 1;
> > > +}
> > > +
> > > +static struct fsl_esdhc_cfg usdhc_cfg[1] = {
> > > +	{USDHC1_BASE_ADDR}
> > > +};
> > > +    
> > 
> > This base address it get from dts.
> >   
> > > +int board_mmc_init(bd_t *bis)
> > > +{
> > > +	//struct src *src_regs = (struct src *)SRC_BASE_ADDR;
> > > +	//u32 val;
> > > +	//u32 port;
> > > +
> > > +	//val = readl(&src_regs->sbmr1);
> > > +
> > > +	/* Boot from USDHC */
> > > +	//port = (val >> 11) & 0x3;
> > > +    
> > 
> > Please correct me if I'm wrong, but such commented code doesn't
> > look like a production one.
> >   
> > > +	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
> > > +
> > > ARRAY_SIZE(usdhc1_pads));
> > > +	//gpio_direction_input(USDHC1_CD_GPIO);
> > > +	usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
> > > +	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> > > +
> > > +	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> > > +	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
> > > +
> > > +
> > > +
> > > +int checkboard(void)
> > > +{
> > > +	puts("Board: DTB iMX6 eval 1a\n");
> > > +
> > > +	return 0;
> > > +}
> > > diff --git a/board/databyte.ch/eval1a/imximage.cfg
> > > b/board/databyte.ch/eval1a/imximage.cfg
> > > new file mode 100644
> > > index 0000000000..21c5026e1f
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/imximage.cfg
> > > @@ -0,0 +1,133 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > + *
> > > + * Refer doc/README.imximage for more details about how-to
> > > configure
> > > + * and create imximage boot image
> > > + *
> > > + * The syntax is taken as close as possible with the kwbimage  */
> > > +
> > > +#define __ASSEMBLY__
> > > +#include <config.h>
> > > +
> > > +/* image version */
> > > +
> > > +IMAGE_VERSION 2
> > > +
> > > +/*
> > > + * Boot Device : one of
> > > + * spi/sd/nand/onenand, qspi/nor
> > > + */
> > > +
> > > +#ifdef CONFIG_QSPI_BOOT
> > > +BOOT_FROM	qspi
> > > +#elif defined(CONFIG_NOR_BOOT)
> > > +BOOT_FROM	nor
> > > +#else
> > > +BOOT_FROM	sd
> > > +#endif
> > > +
> > > +#ifdef CONFIG_USE_IMXIMG_PLUGIN
> > > +/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
> > > +PLUGIN	board/databyte.ch/eval1a/plugin.bin 0x00907000
> > > +#else
> > > +
> > > +#ifdef CONFIG_SECURE_BOOT
> > > +CSF CONFIG_CSF_SIZE
> > > +#endif
> > > +
> > > +/*
> > > + * Device Configuration Data (DCD)
> > > + *
> > > + * Each entry must have the format:
> > > + * Addr-type           Address        Value
> > > + *
> > > + * where:
> > > + *	Addr-type register length (1,2 or 4 bytes)
> > > + *	Address	  absolute address of the register
> > > + *	value	  value to be stored in the register
> > > + */
> > > +
> > > +/* Enable all clocks */
> > > +DATA 4 0x020c4068 0xffffffff
> > > +DATA 4 0x020c406c 0xffffffff
> > > +DATA 4 0x020c4070 0xffffffff
> > > +DATA 4 0x020c4074 0xffffffff
> > > +DATA 4 0x020c4078 0xffffffff
> > > +DATA 4 0x020c407c 0xffffffff
> > > +DATA 4 0x020c4080 0xffffffff
> > > +DATA 4 0x020e04b4 0x000C0000
> > > +DATA 4 0x020e04ac 0x00000000
> > > +DATA 4 0x020e027c 0x00000008
> > > +
> > > +DATA 4 0x020e0250 0x00000008
> > > +DATA 4 0x020e024c 0x00000008
> > > +DATA 4 0x020e0490 0x00000008
> > > +DATA 4 0x020e0288 0x000C0008
> > > +
> > > +DATA 4 0x020e0270 0x00000000
> > > +
> > > +DATA 4 0x020e0260 0x00000008
> > > +DATA 4 0x020e0264 0x00000008
> > > +DATA 4 0x020e04a0 0x00000008
> > > +
> > > +DATA 4 0x020e0494 0x00020000
> > > +DATA 4 0x020e0280 0x00000008
> > > +DATA 4 0x020e0284 0x00000008
> > > +
> > > +DATA 4 0x020e04b0 0x00020000
> > > +DATA 4 0x020e0498 0x00000008
> > > +DATA 4 0x020e04a4 0x00000008
> > > +DATA 4 0x020e0244 0x00000008
> > > +DATA 4 0x020e0248 0x00000008
> > > +
> > > +DATA 4 0x021b001c 0x00008000
> > > +DATA 4 0x021b0800 0xA1390003
> > > +DATA 4 0x021b080c 0x000A0025
> > > +
> > > +DATA 4 0x021b0810 0x000B000B
> > > +DATA 4 0x021b083c 0x014C014C
> > > +DATA 4 0x021b0848 0x40403236
> > > +DATA 4 0x021b0850 0x4040322C
> > > +DATA 4 0x021b081c 0x33333333
> > > +DATA 4 0x021b0820 0x33333333
> > > +
> > > +DATA 4 0x021b082c 0xF3333333
> > > +DATA 4 0x021b0830 0xF3333333
> > > +
> > > +DATA 4 0x021b08c0 0x00944009
> > > +DATA 4 0x021b08b8 0x00000800
> > > +DATA 4 0x021b0004 0x0002002D
> > > +DATA 4 0x021b0008 0x1B333030
> > > +DATA 4 0x021b000c 0x3F4352F3
> > > +DATA 4 0x021b0010 0xB66D0B63
> > > +DATA 4 0x021b0014 0x01FF00DB
> > > +DATA 4 0x021b0018 0x00211740
> > > +
> > > +DATA 4 0x021b001c 0x00008000
> > > +DATA 4 0x021b002c 0x000026D2
> > > +DATA 4 0x021b0030 0x00431023
> > > +
> > > +DATA 4 0x021b0040 0x00000047
> > > +DATA 4 0x021b0000 0x83180000
> > > +DATA 4 0x021b0890 0x00400000
> > > +DATA 4 0x021b001c 0x02008032
> > > +DATA 4 0x021b001c 0x00008033
> > > +
> > > +DATA 4 0x021b001c 0x00408031
> > > +DATA 4 0x021b001c 0x15208030
> > > +DATA 4 0x021b001c 0x04008040
> > > +DATA 4 0x021b001c 0x0200803A
> > > +DATA 4 0x021b001c 0x0000803B
> > > +DATA 4 0x021b001c 0x00408039
> > > +DATA 4 0x021b001c 0x15208038
> > > +DATA 4 0x021b001c 0x04008048
> > > +DATA 4 0x021b0020 0x00007800
> > > +DATA 4 0x021b0818 0x00000117
> > > +DATA 4 0x021b0004 0x0002552D
> > > +DATA 4 0x021b0404 0x00011006
> > > +DATA 4 0x021b001c 0x00000000
> > > +    
> > 
> > What is the purpose of this BCB ? Initial setup shall be done in
> > SPL part of U-Boot.
> >   
> > > +
> > > +#endif
> > > diff --git a/board/databyte.ch/eval1a/plugin.S
> > > b/board/databyte.ch/eval1a/plugin.S
> > > new file mode 100644
> > > index 0000000000..1955c1b3be
> > > --- /dev/null
> > > +++ b/board/databyte.ch/eval1a/plugin.S
> > > @@ -0,0 +1,173 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +/*
> > > + * C Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > + */
> > > +
> > > +#include <config.h>
> > > +
> > > +/* DDR script */
> > > +.macro eval1a_ddr3_setting
> > > +	ldr r0, =IOMUXC_BASE_ADDR
> > > +	ldr r1, =0x000C0000
> > > +	str r1, [r0, #0x4B4]
> > > +
> > > +	ldr r1, =0x00000000
> > > +	str r1, [r0, #0x4AC]
> > > +
> > > +	ldr r1, =0x00000008
> > > +	str r1, [r0, #0x27C]
> > > +	str r1, [r0, #0x250]
> > > +	str r1, [r0, #0x24C]
> > > +	str r1, [r0, #0x490]
> > > +	str r1, [r0, #0x288]
> > > +
> > > +	ldr r1, =0x00000000
> > > +	str r1, [r0, #0x270]
> > > +
> > > +	ldr r1, =0x00000008
> > > +	str r1, [r0, #0x260]
> > > +	str r1, [r0, #0x264]
> > > +	str r1, [r0, #0x4A0]
> > > +
> > > +	ldr r1, =0x00020000
> > > +	str r1, [r0, #0x494]
> > > +
> > > +	ldr r1, =0x00000008
> > > +	str r1, [r0, #0x280]
> > > +	str r1, [r0, #0x284]
> > > +
> > > +	ldr r1, =0x00020000
> > > +	str r1, [r0, #0x4B0]
> > > +
> > > +	ldr r1, =0x00000008
> > > +	str r1, [r0, #0x498]
> > > +	str r1, [r0, #0x4A4]
> > > +	str r1, [r0, #0x244]
> > > +	str r1, [r0, #0x248]
> > > +
> > > +	ldr r0, =MMDC_P0_BASE_ADDR
> > > +	ldr r1, =0x00008000
> > > +	str r1, [r0, #0x1C]
> > > +
> > > +	ldr r1, =0xA1390003
> > > +	str r1, [r0, #0x800]
> > > +
> > > +	ldr r1, =0x000A0025
> > > +	str r1, [r0, #0x80C]
> > > +
> > > +	ldr r1, =0x000B000B
> > > +	str r1, [r0, #0x810]
> > > +
> > > +	ldr r1, =0x014C014C
> > > +	str r1, [r0, #0x83C]
> > > +
> > > +	ldr r1, =0x40403236
> > > +	str r1, [r0, #0x848]
> > > +
> > > +	ldr r1, =0x4040322C
> > > +	str r1, [r0, #0x850]
> > > +	ldr r1, =0x33333333
> > > +	str r1, [r0, #0x81C]
> > > +	str r1, [r0, #0x820]
> > > +	ldr r1, =0xF3333333
> > > +	str r1, [r0, #0x82C]
> > > +	str r1, [r0, #0x830]
> > > +	ldr r1, =0x00944009
> > > +	str r1, [r0, #0x8C0]
> > > +
> > > +	ldr r1, =0x00000800
> > > +	str r1, [r0, #0x8B8]
> > > +	ldr r1, =0x0002002D
> > > +	str r1, [r0, #0x004]
> > > +	ldr r1, =0x1B333030
> > > +	str r1, [r0, #0x008]
> > > +
> > > +	ldr r1, =0x3F4352F3
> > > +	str r1, [r0, #0x00C]
> > > +
> > > +	ldr r1, =0xB66D0B63
> > > +	str r1, [r0, #0x010]
> > > +
> > > +	ldr r1, =0x01FF00DB
> > > +	str r1, [r0, #0x014]
> > > +
> > > +	ldr r1, =0x00211740
> > > +	str r1, [r0, #0x018]
> > > +
> > > +	ldr r1, =0x00008000
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x000026D2
> > > +	str r1, [r0, #0x02C]
> > > +
> > > +	ldr r1, =0x00431023
> > > +	str r1, [r0, #0x030]
> > > +
> > > +	ldr r1, =0x00000047
> > > +	str r1, [r0, #0x040]
> > > +
> > > +	ldr r1, =0x83180000
> > > +	str r1, [r0, #0x000]
> > > +
> > > +	ldr r1, =0x00400000
> > > +	str r1, [r0, #0x890]
> > > +	ldr r1, =0x02008032
> > > +	str r1, [r0, #0x01C]
> > > +	ldr r1, =0x00008033
> > > +	str r1, [r0, #0x01C]
> > > +	ldr r1, =0x00408031
> > > +	str r1, [r0, #0x01C]
> > > +	ldr r1, =0x15208030
> > > +	str r1, [r0, #0x01C]
> > > +	ldr r1, =0x04008040
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x0200803A
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x0000803B
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x00408039
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x15208038
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +	ldr r1, =0x04008048
> > > +	str r1, [r0, #0x01C]
> > > +
> > > +
> > > +	ldr r1, =0x00007800
> > > +	str r1, [r0, #0x020]
> > > +	ldr r1, =0x00000117
> > > +	str r1, [r0, #0x818]
> > > +	ldr r1, =0x0002552D
> > > +	str r1, [r0, #0x004]
> > > +	ldr r1, =0x00011006
> > > +	str r1, [r0, #0x404]
> > > +	ldr r1, =0x00000000
> > > +	str r1, [r0, #0x01C]
> > > +.endm
> > > +
> > > +.macro imx6_clock_gating
> > > +	ldr r0, =CCM_BASE_ADDR
> > > +	ldr r1, =0xFFFFFFFF
> > > +	str r1, [r0, #0x68]
> > > +	str r1, [r0, #0x6C]
> > > +	str r1, [r0, #0x70]
> > > +	str r1, [r0, #0x74]
> > > +	str r1, [r0, #0x78]
> > > +	str r1, [r0, #0x7C]
> > > +	str r1, [r0, #0x80]
> > > +.endm
> > > +
> > > +.macro imx6_qos_setting
> > > +.endm
> > > +
> > > +.macro imx6_ddr_setting
> > > +	eval1a_ddr3_setting
> > > +.endm
> > > +    
> > 
> > i.MX6 now has the code to train and setup ddr automatically.
> >   
> > > +/* include the common plugin code here */ #include 
> > > +<asm/arch/mx6_plugin.S>
> > > diff --git a/configs/eval1a_defconfig b/configs/eval1a_defconfig
> > > new file mode 100644 index 0000000000..64e54b207d
> > > --- /dev/null
> > > +++ b/configs/eval1a_defconfig
> > > @@ -0,0 +1,36 @@
> > > +CONFIG_ARM=y
> > > +CONFIG_ARCH_MX6=y
> > > +CONFIG_TARGET_EVAL1A=y
> > > +CONFIG_MXC_UART=y
> > > +CONFIG_DM_MMC=y
> > > +CONFIG_CMD_FAT=y
> > > +CONFIG_CMD_CACHE=y
> > > +CONFIG_CMD_EXT2=y
> > > +CONFIG_CMD_EXT4=y
> > > +CONFIG_CMD_EXT4_WRITE=y
> > > +CONFIG_CMD_FS_GENERIC=y
> > > +CONFIG_CMD_MMC=y
> > > +CONFIG_CMD_DHCP=y
> > > +CONFIG_CMD_PING=y
> > > +CONFIG_FSL_ESDHC=y
> > > +CONFIG_CMD_BMODE=y
> > > +CONFIG_CMD_BOOTZ=y
> > > +
> > > +CONFIG_SPL_IMAGE="spl/u-boot-spl.bin"
> > > +
> > > +CONFIG_FEC_MXC=y
> > > +CONFIG_CMD_MII=y
> > > +CONFIG_PHYLIB=y
> > > +CONFIG_MII=y
> > > +CONFIG_DM_ETH=y
> > > +CONFIG_ETH=y
> > > +CONFIG_PHY_MICREL=y
> > > +CONFIG_PHY_MICREL_KSZ8XXX=y
> > > +CONFIG_RGMII=y
> > > +CONFIG_NET_RANDOM_ETHADDR=y
> > > +
> > > +CONFIG_DEFAULT_DEVICE_TREE="eval1a"
> > > +
> > > +CONFIG_NR_DRAM_BANKS=1
> > > +
> > > +CONFIG_SYS_TEXT_BASE=0x87800000
> > > diff --git a/include/configs/eval1a.h b/include/configs/eval1a.h
> > > new file mode 100644 index 0000000000..8b75af99e4
> > > --- /dev/null
> > > +++ b/include/configs/eval1a.h
> > > @@ -0,0 +1,54 @@
> > > +#ifndef __EVAL1A_CONFIG_H
> > > +#define __EVAL1A_CONFIG_H
> > > +
> > > +#include "mx6_common.h"
> > > +
> > > +#ifndef CONFIG_MXC_UART
> > > +#define CONFIG_MXC_UART
> > > +#endif
> > > +
> > > +/*
> > > +#define CONFIG_SPL
> > > +#define CONFIG_SPL_BUILD
> > > +#define CONFIG_SPL_FRAMEWORK
> > > +#define CONFIG_SYS_ONENAND_BASE 0x4E000000 #define 
> > > +CONFIG_SPL_TEXT_BASE 0x0 #define CONFIG_SPL_SKIP_RELOCATE
> > > #define +CONFIG_SPL_SERIAL_SUPPORT */
> > > +
> > > +#define CONFIG_ENV_SIZE			SZ_8K
> > > +#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
> > > +
> > > +#define CONFIG_MXC_UART_BASE		UART1_BASE
> > > +
> > > +//#define CONFIG_FEC_MXC
> > > +#define IMX_FEC_BASE			ENET_BASE_ADDR
> > > +#define CONFIG_FEC_XCV_TYPE		RMII
> > > +#define CONFIG_FEC_MXC_PHYADDR		0
> > > +
> > > +
> > > +/* MMC Configs */
> > > +#ifdef CONFIG_FSL_USDHC
> > > +#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
> > > +#endif
> > > +
> > > +#define PHYS_SDRAM_SIZE	SZ_256M
> > > +
> > > +#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
> > > +
> > > +/* Physical Memory Map */
> > > +#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
> > > +
> > > +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
> > > +#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
> > > +#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
> > > +
> > > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > > +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> > > +
> > > +#define CONFIG_SYS_INIT_SP_ADDR \
> > > +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > > +
> > > +
> > > +#endif  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de
> >   
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
> 




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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