[U-Boot] [PATCH 0/5] Virtex2 FPGA enhancements

Michal Simek michal.simek at xilinx.com
Thu Jun 20 11:55:03 UTC 2019

On 19. 06. 19 17:43, Robert Hancock wrote:
> On 2019-06-19 6:10 a.m., Michal Simek wrote:
>> On 18. 06. 19 17:47, Robert Hancock wrote:
>>> These changes add support for slave serial mode, in addition to the
>>> existing slave SelectMAP mode, for programming Xilinx Virtex2 (and later)
>>> FPGAs, as well as fixing up code style and an issue with the programming
>>> sequence.
>>> Robert Hancock (5):
>>>   fpga: virtex2: cosmetic: Cleanup code style
>>>   fpga: virtex2: added Kconfig option
>>>   fpga: virtex2: Split out image writing from pre/post operations
>>>   fpga: virtex2: Add additional clock cycles after DONE assertion
>>>   fpga: virtex2: Add slave serial programming support
>>>  drivers/fpga/Kconfig   |   8 +
>>>  drivers/fpga/virtex2.c | 503 +++++++++++++++++++++++++++++--------------------
>>>  include/virtex2.h      |  13 +-
>>>  3 files changed, 313 insertions(+), 211 deletions(-)
>> I have not a problem with this code but my question is what's your plan
>> about it? Right now none is really calling/building this code.
>> Are you going to push any platform which will enable this driver?
> This is being used on an internal platform that hasn't been upstreamed
> yet. There is some more cleanup that needs to happen in the board code
> before that can happen but I think we could potentially do that.
> However, now that there is a Kconfig option for this it would be a lot
> easier for those code to be built for other platforms that will use it.

It will be useful to have this code available because of fpga functions
needs to be implemented based on your connection. Do you have this in
any internal repo or also available in your u-boot clone somewhere like


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