[U-Boot] [PATCH v2 2/2] xilinx_xiic: Fix transfer initialisation
marex at denx.de
Wed Jun 26 09:46:17 UTC 2019
On 6/26/19 7:30 AM, Melin Tomas wrote:
> On 6/25/19 6:15 PM, Marek Vasut wrote:
>> On 6/25/19 3:30 PM, Melin Tomas wrote:
>>> Prior to starting a new transfer, conditionally wait for bus to not
>>> be busy.
>>> Reinitialise controller as otherwise operation is not stable.
>>> For reference, see linux kernel commit: 9656eeebf3f1 ("i2c: Revert
>>> "i2c: xiic: Do not reset controller before every transfer"")
>>> Signed-off-by: Tomas Melin <tomas.melin at vaisala.com>
>>> Changes in v2:
>>> - Change variable declaration order
>>> - Change timeout to 3ms
>> Why 3mS ?
> That is value used also in kernel driver.
But why 3mS , why not e.g. 5mS ?
More information about the U-Boot