[U-Boot] [PATCH 3/5] ARM: socfpga: vining_fpga: Update generated headers
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Thu Jun 27 09:33:24 UTC 2019
On Thu, Jun 27, 2019 at 12:21 AM Marek Vasut <marex at denx.de> wrote:
>
> Update headers generated by quartus to the latest version.
Would it be good to add the version you used?
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Silvio Fricke <silvio.fricke at softing.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> ---
> board/softing/vining_fpga/qts/iocsr_config.h | 140 +++++++++---------
> board/softing/vining_fpga/qts/pinmux_config.h | 6 +-
> board/softing/vining_fpga/qts/pll_config.h | 12 +-
> board/softing/vining_fpga/qts/sdram_config.h | 12 +-
> 4 files changed, 82 insertions(+), 88 deletions(-)
>
> diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h
> index 1fe2a09e56..8c78aecdd3 100644
> --- a/board/softing/vining_fpga/qts/iocsr_config.h
> +++ b/board/softing/vining_fpga/qts/iocsr_config.h
> @@ -139,9 +139,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x07900000,
> 0x08020000,
> 0x00100000,
> - 0xC8800000,
> - 0x00003001,
> - 0x00C00722,
> + 0xD4380000,
> + 0xE0003000,
> + 0x00C00350,
> 0x00000000,
> 0x00000021,
> 0x82000004,
> @@ -153,10 +153,10 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x03C80000,
> 0x05400000,
> 0x03C80000,
> - 0xE4400000,
> - 0x00001800,
> - 0x00600391,
> - 0x800E4400,
> + 0x6A1C0000,
> + 0x70001800,
> + 0x006001A8,
> + 0x8006A1C0,
> 0x00000001,
> 0x40000002,
> 0x02A00000,
> @@ -167,11 +167,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x01E40000,
> 0x02A00000,
> 0x01E40000,
> - 0x72200000,
> - 0x80000C00,
> - 0x003001C8,
> - 0xC0072200,
> - 0x1C880000,
> + 0x350E0000,
> + 0x38000C00,
> + 0x003000D4,
> + 0xC00350E0,
> + 0x0D438000,
> 0x20000300,
> 0x00040000,
> 0x50670000,
> @@ -200,9 +200,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x15000000,
> 0x0F200000,
> 0x01FE0000,
> - 0x00000000,
> - 0x01800E44,
> - 0x00391000,
> + 0xC0000000,
> + 0x018006A1,
> + 0x001A8700,
> 0x007F8006,
> 0x00000000,
> 0x0A800001,
> @@ -213,11 +213,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x07900000,
> 0x08020000,
> 0x00100000,
> - 0xC8800000,
> - 0x00003001,
> - 0x00C00722,
> + 0xD4380000,
> + 0xE0003000,
> + 0x00C00350,
> 0x00000FF0,
> - 0x72200000,
> + 0x350E0000,
> 0x80000C00,
> 0x05400000,
> 0x02480000,
> @@ -228,9 +228,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x05400000,
> 0x03C80000,
> 0x6A1C0000,
> - 0x00001800,
> - 0x00600391,
> - 0x800E4400,
> + 0x70001800,
> + 0x006001A8,
> + 0x8006A1C0,
> 0x1A870001,
> 0x40000600,
> 0x02A00040,
> @@ -241,11 +241,11 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x01E40000,
> 0x02A00000,
> 0x01E40000,
> - 0x72200000,
> - 0x80000C00,
> - 0x003001C8,
> - 0xC0072200,
> - 0x1C880000,
> + 0x350E0000,
> + 0x38000C00,
> + 0x003000D4,
> + 0xC00350E0,
> + 0x0D438000,
> 0x20000300,
> 0x00040000,
> 0x50670000,
> @@ -262,9 +262,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x01A00040,
> 0x280D0002,
> 0x5140680A,
> - 0x02490340,
> - 0xD012481A,
> - 0x0680A280,
> + 0x01450340,
> + 0xD00A281A,
> + 0x0680E380,
> 0x10040000,
> 0x00200000,
> 0x10040000,
> @@ -274,9 +274,9 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x15000000,
> 0x0F200000,
> 0x01FE0000,
> - 0x00000000,
> - 0x01800E44,
> - 0x00391000,
> + 0xC0000000,
> + 0x018006A1,
> + 0x001A8700,
> 0x007F8006,
> 0x00000000,
> 0x99300001,
> @@ -304,8 +304,8 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x5506A000,
> 0x00E1D400,
> 0x00000000,
> - 0xC880090C,
> - 0x00003001,
> + 0xD438090C,
> + 0x00003000,
> 0x90400000,
> 0x00000000,
> 0x2020C243,
> @@ -325,22 +325,22 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x00104120,
> 0x00000200,
> 0xAC0D5F80,
> - 0x7FFFFFFF,
> - 0x14F36080,
> - 0x1A041404,
> + 0xFFFFFFFF,
> + 0x14F3690D,
> + 0x1A041414,
> 0x00D00000,
> 0x14864000,
> 0x59647A05,
> - 0x8A28A3D5,
> + 0x8A28A3DD,
> 0xF6D1451E,
> 0x034AD348,
> 0x821A0000,
> 0x0000D000,
> 0x05140680,
> - 0xD569A47A,
> + 0xDD59647A,
> 0x1E8A28A3,
> 0x48F6D145,
> - 0x00035292,
> + 0x00034AD3,
> 0x00080200,
> 0x00001000,
> 0x00080200,
> @@ -393,27 +393,27 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x0000F200,
> 0x00000000,
> 0x00000482,
> - 0x00120800,
> - 0x00600391,
> + 0x70120800,
> + 0x006001A8,
> 0x80000000,
> 0x00104120,
> 0x00000200,
> 0xAC0D5F80,
> - 0x7FFFFFFF,
> - 0x14F36080,
> - 0x1A041404,
> + 0xFFFFFFFF,
> + 0x14F3690D,
> + 0x1A041414,
> 0x00D00000,
> 0x14864000,
> 0x59647A05,
> - 0x8A28A3D5,
> - 0xF4D1451E,
> + 0x8A28A3DD,
> + 0xF6D1451E,
> 0x034AD348,
> 0x821A0186,
> 0x0000D000,
> 0x00000680,
> - 0xD569A47A,
> - 0x1EF228A3,
> - 0x48F4D145,
> + 0xDD59647A,
> + 0x1E8A28A3,
> + 0x48F6D145,
> 0x00034AD3,
> 0x00080200,
> 0x00001000,
> @@ -452,8 +452,8 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x5506A000,
> 0x00E1D400,
> 0x00000000,
> - 0xC880090C,
> - 0x00003001,
> + 0xD438090C,
> + 0x00003000,
> 0x90400000,
> 0x00000000,
> 0x2020C243,
> @@ -473,21 +473,21 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x00104120,
> 0x00000200,
> 0xAC0D5F80,
> - 0x7FFFFFFF,
> - 0x14F36080,
> - 0x1A041404,
> + 0xFFFFFFFF,
> + 0x14F3690D,
> + 0x1A041414,
> 0x00D00000,
> - 0x0C864000,
> - 0x59647A03,
> - 0xCB2CA3DD,
> - 0xF6D9651E,
> + 0x14864000,
> + 0x59647A05,
> + 0x8A28A3DD,
> + 0xF6D1451E,
> 0x034AD348,
> 0x821A0000,
> 0x0000D000,
> 0x00000680,
> 0xDD59647A,
> 0x1E8A28A3,
> - 0x48F6D965,
> + 0x48F6D145,
> 0x00034AD3,
> 0x00080200,
> 0x00001000,
> @@ -547,19 +547,19 @@ const unsigned long iocsr_scan_chain3_table[] = {
> 0x00104120,
> 0x00000200,
> 0xAC0D5F80,
> - 0x7FFFFFFF,
> - 0x14F16080,
> - 0x1A041404,
> + 0xFFFFFFFF,
> + 0x14F1690D,
> + 0x1A041414,
> 0x00D00000,
> - 0x04864000,
> - 0x69A47A01,
> - 0xF228A3D5,
> - 0xF4D1451E,
> - 0x03529248,
> + 0x14864000,
> + 0x59647A05,
> + 0x8A28A3DD,
> + 0xF6D1451E,
> + 0x034AD348,
> 0x821A0000,
> 0x0000D000,
> 0x00000680,
> - 0xD559647A,
> + 0xDD59647A,
> 0x1E8A28A3,
> 0x48F6D145,
> 0x00034AD3,
> diff --git a/board/softing/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h
> index 40b89123ec..f73ccbbabe 100644
> --- a/board/softing/vining_fpga/qts/pinmux_config.h
> +++ b/board/softing/vining_fpga/qts/pinmux_config.h
> @@ -198,12 +198,12 @@ const u8 sys_mgr_init_table[] = {
> 0, /* NANDUSEFPGA */
> 0, /* UART0USEFPGA */
> 0, /* RGMII1USEFPGA */
> - 1, /* SPIS0USEFPGA */
> + 0, /* SPIS0USEFPGA */
> 0, /* CAN0USEFPGA */
> 0, /* I2C0USEFPGA */
> 0, /* SDMMCUSEFPGA */
> 0, /* QSPIUSEFPGA */
> - 1, /* SPIS1USEFPGA */
> + 0, /* SPIS1USEFPGA */
> 1, /* RGMII0USEFPGA */
> 0, /* UART1USEFPGA */
> 0, /* CAN1USEFPGA */
> @@ -211,7 +211,7 @@ const u8 sys_mgr_init_table[] = {
> 0, /* I2C3USEFPGA */
> 0, /* I2C2USEFPGA */
> 0, /* I2C1USEFPGA */
> - 0, /* SPIM1USEFPGA */
> + 1, /* SPIM1USEFPGA */
> 0, /* USB0USEFPGA */
> 0 /* SPIM0USEFPGA */
> };
> diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h
> index 5d2a08ba00..fa04618336 100644
> --- a/board/softing/vining_fpga/qts/pll_config.h
> +++ b/board/softing/vining_fpga/qts/pll_config.h
> @@ -13,7 +13,7 @@
> #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
> #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
> #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
> -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
> +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
> #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
> #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
> #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
> @@ -53,7 +53,7 @@
> #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
> #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
> #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
> -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
> +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
> #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
>
> #define CONFIG_HPS_CLK_OSC1_HZ 25000000
> @@ -63,18 +63,12 @@
> #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
> #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
> -#define CONFIG_HPS_CLK_OSC1_HZ 25000000
> -#define CONFIG_HPS_CLK_OSC2_HZ 25000000
> -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
> -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
> -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
> -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
> #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> #define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
> #define CONFIG_HPS_CLK_NAND_HZ 488281
> #define CONFIG_HPS_CLK_SDMMC_HZ 1953125
> -#define CONFIG_HPS_CLK_QSPI_HZ 400000000
> +#define CONFIG_HPS_CLK_QSPI_HZ 320000000
> #define CONFIG_HPS_CLK_SPIM_HZ 200000000
> #define CONFIG_HPS_CLK_CAN0_HZ 12500000
> #define CONFIG_HPS_CLK_CAN1_HZ 12500000
> diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h
> index de9f0e4153..ec067eb473 100644
> --- a/board/softing/vining_fpga/qts/sdram_config.h
> +++ b/board/softing/vining_fpga/qts/sdram_config.h
> @@ -47,7 +47,7 @@
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
> #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
> #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
> #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
> @@ -62,15 +62,15 @@
> #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
> #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
> #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
> -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
> +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
> #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
> #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
> #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
> #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
> -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
> -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
> +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
> +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
> #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
> -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
> +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
> #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
> #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
> #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
> @@ -149,7 +149,7 @@
> #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
> #define MAX_LATENCY_COUNT_WIDTH 5
> #define READ_VALID_FIFO_SIZE 16
> -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
> +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b4
> #define RW_MGR_MEM_ADDRESS_MIRRORING 0
> #define RW_MGR_MEM_DATA_MASK_WIDTH 4
> #define RW_MGR_MEM_DATA_WIDTH 32
> --
> 2.20.1
>
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