[U-Boot] [PATCH v4 03/17] arm: socfpga: Move Stratix10 and Agilex reset manager common code
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Wed Oct 2 08:24:42 UTC 2019
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h.
>
> Remove unused RSTMGR_XXX defines.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>
> ---
> v4:
> - Change prefix from RSTMGR_S10* to RSTMGR_SOC64*.
>
> v3:
> - Add new reset_manager_soc64.h
> - Convert to use defines instead of struct.
> ---
> .../include/mach/reset_manager_s10.h | 87 +------------------
> .../include/mach/reset_manager_soc64.h | 38 ++++++++
> arch/arm/mach-socfpga/reset_manager_s10.c | 20 ++---
> 3 files changed, 50 insertions(+), 95 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> index b602129656..fdc9c8c9a4 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> @@ -1,95 +1,12 @@
> /* SPDX-License-Identifier: GPL-2.0
> *
> - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> *
> */
>
> #ifndef _RESET_MANAGER_S10_
> #define _RESET_MANAGER_S10_
>
> -void reset_cpu(ulong addr);
> -int cpu_has_been_warmreset(void);
> -
> -void socfpga_bridges_reset(int enable);
> -
> -void socfpga_per_reset(u32 reset, int set);
> -void socfpga_per_reset_all(void);
> -
> -#define RSTMGR_S10_STATUS 0
> -#define RSTMGR_S10_MPUMODRST 0x20
> -#define RSTMGR_S10_PER0MODRST 0x24
> -#define RSTMGR_S10_PER1MODRST 0x28
> -#define RSTMGR_S10_BRGMODRST 0x2c
> -
> -#define RSTMGR_MPUMODRST_CORE0 0
> -#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
> -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
> -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
> -
> -/* Watchdogs and MPU warm reset mask */
> -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
> -
> -/*
> - * Define a reset identifier, from which a permodrst bank ID
> - * and reset ID can be extracted using the subsequent macros
> - * RSTMGR_RESET() and RSTMGR_BANK().
> - */
> -#define RSTMGR_BANK_OFFSET 8
> -#define RSTMGR_BANK_MASK 0x7
> -#define RSTMGR_RESET_OFFSET 0
> -#define RSTMGR_RESET_MASK 0x1f
> -#define RSTMGR_DEFINE(_bank, _offset) \
> - ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
> -
> -/* Extract reset ID from the reset identifier. */
> -#define RSTMGR_RESET(_reset) \
> - (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
> -
> -/* Extract bank ID from the reset identifier. */
> -#define RSTMGR_BANK(_reset) \
> - (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
> -
> -/*
> - * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
> - * 0 ... mpumodrst
> - * 1 ... per0modrst
> - * 2 ... per1modrst
> - * 3 ... brgmodrst
> - */
> -#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
> -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
> -#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
> -#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
> -#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
> -#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
> -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
> -#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
> -#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
> -#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
> -#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
> -#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
> -#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
> -#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
> -#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
> -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
> -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
> -#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
> -#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
> -#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
> -#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
> -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
> -#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
> -#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
> -#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
> -#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
> -#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
> -#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
> -#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
> -#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
> -#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
> -#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
> -
> -/* Create a human-readable reference to SoCFPGA reset. */
> -#define SOCFPGA_RESET(_name) RSTMGR_##_name
> +#include <asm/arch/reset_manager_soc64.h>
>
> #endif /* _RESET_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
> new file mode 100644
> index 0000000000..3b739a0202
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
> + */
> +
> +#ifndef _RESET_MANAGER_SOC64_H_
> +#define _RESET_MANAGER_SOC64_H_
> +
> +void reset_deassert_peripherals_handoff(void);
> +int cpu_has_been_warmreset(void);
> +void socfpga_bridges_reset(int enable);
> +
> +#define RSTMGR_SOC64_STATUS 0
> +#define RSTMGR_SOC64_MPUMODRST 0x20
> +#define RSTMGR_SOC64_PER0MODRST 0x24
> +#define RSTMGR_SOC64_PER1MODRST 0x28
> +#define RSTMGR_SOC64_BRGMODRST 0x2c
> +
> +#define RSTMGR_MPUMODRST_CORE0 0
> +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
> +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
> +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
> +
> +/* Watchdogs and MPU warm reset mask */
> +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
> +
> +/*
> + * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
> + * 0 ... mpumodrst
> + * 1 ... per0modrst
> + * 2 ... per1modrst
> + * 3 ... brgmodrst
> + */
> +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
> +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
> +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
> +
> +#endif /* _RESET_MANAGER_SOC64_H_ */
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> index 50a2d80930..bdc0f3ee6e 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -18,13 +18,13 @@ void socfpga_per_reset(u32 reset, int set)
> unsigned long reg;
>
> if (RSTMGR_BANK(reset) == 0)
> - reg = RSTMGR_S10_MPUMODRST;
> + reg = RSTMGR_SOC64_MPUMODRST;
> else if (RSTMGR_BANK(reset) == 1)
> - reg = RSTMGR_S10_PER0MODRST;
> + reg = RSTMGR_SOC64_PER0MODRST;
> else if (RSTMGR_BANK(reset) == 2)
> - reg = RSTMGR_S10_PER1MODRST;
> + reg = RSTMGR_SOC64_PER1MODRST;
> else if (RSTMGR_BANK(reset) == 3)
> - reg = RSTMGR_S10_BRGMODRST;
> + reg = RSTMGR_SOC64_BRGMODRST;
> else /* Invalid reset register, do nothing */
> return;
>
> @@ -47,9 +47,9 @@ void socfpga_per_reset_all(void)
>
> /* disable all except OCP and l4wd0. OCP disable later */
> writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
> - socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> - writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> - writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
> + socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST);
> + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST);
> + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_SOC64_PER1MODRST);
> }
>
> void socfpga_bridges_reset(int enable)
> @@ -60,7 +60,7 @@ void socfpga_bridges_reset(int enable)
> ~0);
>
> /* Release all bridges from reset state */
> - clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
> + clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0);
>
> /* Poll until all idleack to 0 */
> while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
> @@ -83,7 +83,7 @@ void socfpga_bridges_reset(int enable)
> ;
>
> /* Reset all bridges (except NOR DDR scheduler & F2S) */
> - setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST,
> ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
> RSTMGR_BRGMODRST_FPGA2SOC_MASK));
>
> @@ -97,6 +97,6 @@ void socfpga_bridges_reset(int enable)
> */
> int cpu_has_been_warmreset(void)
> {
> - return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
> + return readl(socfpga_rstmgr_base + RSTMGR_SOC64_STATUS) &
> RSTMGR_L4WD_MPU_WARMRESET_MASK;
> }
> --
> 2.19.0
>
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