[U-Boot] [PATCH v4 05/17] arm: socfpga: Move Stratix10 and Agilex system manager common code

Simon Goldschmidt simon.k.r.goldschmidt at gmail.com
Wed Oct 2 08:26:54 UTC 2019


On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> Move Stratix10 and Agilex system manager common code to system_manager_soc64.h.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>

>
> ---
> v4:
> - Change prefix from SYSMGR_S10* to SYSMGR_SOC64*.
>
> v3:
> - Change filename to system_manager_soc64.h
> - Move to use defines instead of struct.
>
> v2:
> - Move common defines for Stratix 10 and Agilex to system_manager_s10_agilex_common.h
> ---
>  arch/arm/mach-socfpga/clock_manager_s10.c     |   2 +-
>  arch/arm/mach-socfpga/firewall.c              |   4 +-
>  .../include/mach/system_manager_s10.h         | 116 +----------------
>  .../include/mach/system_manager_soc64.h       | 123 ++++++++++++++++++
>  arch/arm/mach-socfpga/mailbox_s10.c           |   2 +-
>  arch/arm/mach-socfpga/misc_s10.c              |   4 +-
>  arch/arm/mach-socfpga/reset_manager_s10.c     |  14 +-
>  arch/arm/mach-socfpga/spl_s10.c               |   2 +-
>  arch/arm/mach-socfpga/system_manager_s10.c    |  26 ++--
>  arch/arm/mach-socfpga/wrap_pll_config_s10.c   |   8 +-
>  drivers/ddr/altera/sdram_s10.c                |   2 +-
>  11 files changed, 157 insertions(+), 146 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> index c6269701f0..bae07e02b6 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -382,7 +382,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
>  unsigned int cm_get_qspi_controller_clk_hz(void)
>  {
> -       return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> +       return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>  }
>
>  unsigned int cm_get_spi_controller_clk_hz(void)
> diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
> index 7c9d317896..c32a7c84b5 100644
> --- a/arch/arm/mach-socfpga/firewall.c
> +++ b/arch/arm/mach-socfpga/firewall.c
> @@ -101,7 +101,7 @@ void firewall_setup(void)
>
>         /* enable non-secure interface to DMA330 DMA and peripherals */
>         writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
> -              socfpga_sysmgr_base + SYSMGR_S10_DMA);
> +              socfpga_sysmgr_base + SYSMGR_SOC64_DMA);
>         writel(SYSMGR_DMAPERIPH_ALL_NS,
> -              socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
> +              socfpga_sysmgr_base + SYSMGR_SOC64_DMA_PERIPH);
>  }
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> index e68a8e730e..c537fb300c 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> @@ -1,124 +1,12 @@
>  /* SPDX-License-Identifier: GPL-2.0
>   *
> - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
>   *
>   */
>
>  #ifndef        _SYSTEM_MANAGER_S10_
>  #define        _SYSTEM_MANAGER_S10_
>
> -void sysmgr_pinmux_init(void);
> -void populate_sysmgr_fpgaintf_module(void);
> -void populate_sysmgr_pinmux(void);
> -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
> -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
> -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
> -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
> -
> -#define SYSMGR_S10_WDDBG                       0x8
> -#define SYSMGR_S10_DMA                         0x20
> -#define SYSMGR_S10_DMA_PERIPH                  0x24
> -#define SYSMGR_S10_SDMMC                       0x28
> -#define SYSMGR_S10_SDMMC_L3MASTER              0x2c
> -#define SYSMGR_S10_EMAC_GLOBAL                 0x40
> -#define SYSMGR_S10_EMAC0                       0x44
> -#define SYSMGR_S10_EMAC1                       0x48
> -#define SYSMGR_S10_EMAC2                       0x4c
> -#define SYSMGR_S10_EMAC0_ACE                   0x50
> -#define SYSMGR_S10_EMAC1_ACE                   0x54
> -#define SYSMGR_S10_EMAC2_ACE                   0x58
> -#define SYSMGR_S10_NAND_AXUSER                 0x5c
> -#define SYSMGR_S10_FPGAINTF_EN1                        0x68
> -#define SYSMGR_S10_FPGAINTF_EN2                        0x6c
> -#define SYSMGR_S10_FPGAINTF_EN3                        0x70
> -#define SYSMGR_S10_DMA_L3MASTER                        0x74
> -#define SYSMGR_S10_HMC_CLK                     0xb4
> -#define SYSMGR_S10_IO_PA_CTRL                  0xb8
> -#define SYSMGR_S10_NOC_TIMEOUT                 0xc0
> -#define SYSMGR_S10_NOC_IDLEREQ_SET             0xc4
> -#define SYSMGR_S10_NOC_IDLEREQ_CLR             0xc8
> -#define SYSMGR_S10_NOC_IDLEREQ_VAL             0xcc
> -#define SYSMGR_S10_NOC_IDLEACK                 0xd0
> -#define SYSMGR_S10_NOC_IDLESTATUS              0xd4
> -#define SYSMGR_S10_FPGA2SOC_CTRL               0xd8
> -#define SYSMGR_S10_FPGA_CONFIG                 0xdc
> -#define SYSMGR_S10_IOCSRCLK_GATE               0xe0
> -#define SYSMGR_S10_GPO                         0xe4
> -#define SYSMGR_S10_GPI                         0xe8
> -#define SYSMGR_S10_MPU                         0xf0
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD0          0x200
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD1          0x204
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD2          0x208
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD3          0x20c
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD4          0x210
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD5          0x214
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD6          0x218
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD7          0x21c
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD8          0x220
> -#define SYSMGR_S10_BOOT_SCRATCH_COLD9          0x224
> -#define SYSMGR_S10_PINSEL0                     0x1000
> -#define SYSMGR_S10_IOCTRL0                     0x1130
> -#define SYSMGR_S10_EMAC0_USEFPGA               0x1300
> -#define SYSMGR_S10_EMAC1_USEFPGA               0x1304
> -#define SYSMGR_S10_EMAC2_USEFPGA               0x1308
> -#define SYSMGR_S10_I2C0_USEFPGA                        0x130c
> -#define SYSMGR_S10_I2C1_USEFPGA                        0x1310
> -#define SYSMGR_S10_I2C_EMAC0_USEFPGA           0x1314
> -#define SYSMGR_S10_I2C_EMAC1_USEFPGA           0x1318
> -#define SYSMGR_S10_I2C_EMAC2_USEFPGA           0x131c
> -#define SYSMGR_S10_NAND_USEFPGA                        0x1320
> -#define SYSMGR_S10_SPIM0_USEFPGA               0x1328
> -#define SYSMGR_S10_SPIM1_USEFPGA               0x132c
> -#define SYSMGR_S10_SPIS0_USEFPGA               0x1330
> -#define SYSMGR_S10_SPIS1_USEFPGA               0x1334
> -#define SYSMGR_S10_UART0_USEFPGA               0x1338
> -#define SYSMGR_S10_UART1_USEFPGA               0x133c
> -#define SYSMGR_S10_MDIO0_USEFPGA               0x1340
> -#define SYSMGR_S10_MDIO1_USEFPGA               0x1344
> -#define SYSMGR_S10_MDIO2_USEFPGA               0x1348
> -#define SYSMGR_S10_JTAG_USEFPGA                        0x1350
> -#define SYSMGR_S10_SDMMC_USEFPGA               0x1354
> -#define SYSMGR_S10_HPS_OSC_CLK                 0x1358
> -#define SYSMGR_S10_IODELAY0                    0x1400
> -
> -#define SYSMGR_SDMMC                           SYSMGR_S10_SDMMC
> -
> -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX        BIT(0)
> -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO    BIT(1)
> -#define SYSMGR_ECC_OCRAM_EN    BIT(0)
> -#define SYSMGR_ECC_OCRAM_SERR  BIT(3)
> -#define SYSMGR_ECC_OCRAM_DERR  BIT(4)
> -#define SYSMGR_FPGAINTF_USEFPGA        0x1
> -
> -#define SYSMGR_FPGAINTF_NAND   BIT(4)
> -#define SYSMGR_FPGAINTF_SDMMC  BIT(8)
> -#define SYSMGR_FPGAINTF_SPIM0  BIT(16)
> -#define SYSMGR_FPGAINTF_SPIM1  BIT(24)
> -#define SYSMGR_FPGAINTF_EMAC0  BIT(0)
> -#define SYSMGR_FPGAINTF_EMAC1  BIT(8)
> -#define SYSMGR_FPGAINTF_EMAC2  BIT(16)
> -
> -#define SYSMGR_SDMMC_SMPLSEL_SHIFT     4
> -#define SYSMGR_SDMMC_DRVSEL_SHIFT      0
> -
> -/* EMAC Group Bit definitions */
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII       0x0
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII          0x1
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII           0x2
> -
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB                        0
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB                        2
> -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                        0x3
> -
> -#define SYSMGR_NOC_H2F_MSK             0x00000001
> -#define SYSMGR_NOC_LWH2F_MSK           0x00000010
> -#define SYSMGR_HMC_CLK_STATUS_MSK      0x00000001
> -
> -#define SYSMGR_DMA_IRQ_NS              0xFF000000
> -#define SYSMGR_DMA_MGR_NS              0x00010000
> -
> -#define SYSMGR_DMAPERIPH_ALL_NS                0xFFFFFFFF
> -
> -#define SYSMGR_WDDBG_PAUSE_ALL_CPU     0x0F0F0F0F
> +#include <asm/arch/system_manager_soc64.h>
>
>  #endif /* _SYSTEM_MANAGER_S10_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> new file mode 100644
> index 0000000000..c09e4ee19c
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 Intel Corporation <www.intel.com>
> + */
> +
> +#ifndef _SYSTEM_MANAGER_SOC64_H_
> +#define _SYSTEM_MANAGER_SOC64_H_
> +
> +void sysmgr_pinmux_init(void);
> +void populate_sysmgr_fpgaintf_module(void);
> +void populate_sysmgr_pinmux(void);
> +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
> +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
> +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
> +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
> +
> +#define SYSMGR_SOC64_WDDBG                     0x8
> +#define SYSMGR_SOC64_DMA                       0x20
> +#define SYSMGR_SOC64_DMA_PERIPH                        0x24
> +#define SYSMGR_SOC64_SDMMC                     0x28
> +#define SYSMGR_SOC64_SDMMC_L3MASTER            0x2c
> +#define SYSMGR_SOC64_EMAC_GLOBAL               0x40
> +#define SYSMGR_SOC64_EMAC0                     0x44
> +#define SYSMGR_SOC64_EMAC1                     0x48
> +#define SYSMGR_SOC64_EMAC2                     0x4c
> +#define SYSMGR_SOC64_EMAC0_ACE                 0x50
> +#define SYSMGR_SOC64_EMAC1_ACE                 0x54
> +#define SYSMGR_SOC64_EMAC2_ACE                 0x58
> +#define SYSMGR_SOC64_NAND_AXUSER               0x5c
> +#define SYSMGR_SOC64_FPGAINTF_EN1              0x68
> +#define SYSMGR_SOC64_FPGAINTF_EN2              0x6c
> +#define SYSMGR_SOC64_FPGAINTF_EN3              0x70
> +#define SYSMGR_SOC64_DMA_L3MASTER              0x74
> +#define SYSMGR_SOC64_HMC_CLK                   0xb4
> +#define SYSMGR_SOC64_IO_PA_CTRL                        0xb8
> +#define SYSMGR_SOC64_NOC_TIMEOUT               0xc0
> +#define SYSMGR_SOC64_NOC_IDLEREQ_SET           0xc4
> +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR           0xc8
> +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL           0xcc
> +#define SYSMGR_SOC64_NOC_IDLEACK               0xd0
> +#define SYSMGR_SOC64_NOC_IDLESTATUS            0xd4
> +#define SYSMGR_SOC64_FPGA2SOC_CTRL             0xd8
> +#define SYSMGR_SOC64_FPGA_CONFIG               0xdc
> +#define SYSMGR_SOC64_IOCSRCLK_GATE             0xe0
> +#define SYSMGR_SOC64_GPO                       0xe4
> +#define SYSMGR_SOC64_GPI                       0xe8
> +#define SYSMGR_SOC64_MPU                       0xf0
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0                0x200
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1                0x204
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2                0x208
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3                0x20c
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4                0x210
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5                0x214
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6                0x218
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7                0x21c
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8                0x220
> +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9                0x224
> +#define SYSMGR_SOC64_PINSEL0                   0x1000
> +#define SYSMGR_SOC64_IOCTRL0                   0x1130
> +#define SYSMGR_SOC64_EMAC0_USEFPGA             0x1300
> +#define SYSMGR_SOC64_EMAC1_USEFPGA             0x1304
> +#define SYSMGR_SOC64_EMAC2_USEFPGA             0x1308
> +#define SYSMGR_SOC64_I2C0_USEFPGA              0x130c
> +#define SYSMGR_SOC64_I2C1_USEFPGA              0x1310
> +#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA         0x1314
> +#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA         0x1318
> +#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA         0x131c
> +#define SYSMGR_SOC64_NAND_USEFPGA              0x1320
> +#define SYSMGR_SOC64_SPIM0_USEFPGA             0x1328
> +#define SYSMGR_SOC64_SPIM1_USEFPGA             0x132c
> +#define SYSMGR_SOC64_SPIS0_USEFPGA             0x1330
> +#define SYSMGR_SOC64_SPIS1_USEFPGA             0x1334
> +#define SYSMGR_SOC64_UART0_USEFPGA             0x1338
> +#define SYSMGR_SOC64_UART1_USEFPGA             0x133c
> +#define SYSMGR_SOC64_MDIO0_USEFPGA             0x1340
> +#define SYSMGR_SOC64_MDIO1_USEFPGA             0x1344
> +#define SYSMGR_SOC64_MDIO2_USEFPGA             0x1348
> +#define SYSMGR_SOC64_JTAG_USEFPGA              0x1350
> +#define SYSMGR_SOC64_SDMMC_USEFPGA             0x1354
> +#define SYSMGR_SOC64_HPS_OSC_CLK               0x1358
> +#define SYSMGR_SOC64_IODELAY0                  0x1400
> +
> +#define SYSMGR_SDMMC                           SYSMGR_SOC64_SDMMC
> +
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX        BIT(0)
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO    BIT(1)
> +#define SYSMGR_ECC_OCRAM_EN    BIT(0)
> +#define SYSMGR_ECC_OCRAM_SERR  BIT(3)
> +#define SYSMGR_ECC_OCRAM_DERR  BIT(4)
> +#define SYSMGR_FPGAINTF_USEFPGA        0x1
> +
> +#define SYSMGR_FPGAINTF_NAND   BIT(4)
> +#define SYSMGR_FPGAINTF_SDMMC  BIT(8)
> +#define SYSMGR_FPGAINTF_SPIM0  BIT(16)
> +#define SYSMGR_FPGAINTF_SPIM1  BIT(24)
> +#define SYSMGR_FPGAINTF_EMAC0  BIT(0)
> +#define SYSMGR_FPGAINTF_EMAC1  BIT(8)
> +#define SYSMGR_FPGAINTF_EMAC2  BIT(16)
> +
> +#define SYSMGR_SDMMC_SMPLSEL_SHIFT     4
> +#define SYSMGR_SDMMC_DRVSEL_SHIFT      0
> +
> +/* EMAC Group Bit definitions */
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII       0x0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII          0x1
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII           0x2
> +
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB                        0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB                        2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                        0x3
> +
> +#define SYSMGR_NOC_H2F_MSK             0x00000001
> +#define SYSMGR_NOC_LWH2F_MSK           0x00000010
> +#define SYSMGR_HMC_CLK_STATUS_MSK      0x00000001
> +
> +#define SYSMGR_DMA_IRQ_NS              0xFF000000
> +#define SYSMGR_DMA_MGR_NS              0x00010000
> +
> +#define SYSMGR_DMAPERIPH_ALL_NS                0xFFFFFFFF
> +
> +#define SYSMGR_WDDBG_PAUSE_ALL_CPU     0x0F0F0F0F
> +
> +#endif /* _SYSTEM_MANAGER_SOC64_H_ */
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> index 11b57361c7..ba81461f90 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -316,7 +316,7 @@ int mbox_qspi_open(void)
>         /* We are getting QSPI ref clock and set into sysmgr boot register */
>         printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
>         writel(resp_buf[0],
> -              socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> +              socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>
>         return 0;
>
> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> index 16fbf71599..ba95ab566b 100644
> --- a/arch/arm/mach-socfpga/misc_s10.c
> +++ b/arch/arm/mach-socfpga/misc_s10.c
> @@ -65,8 +65,8 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
>         else
>                 return -EINVAL;
>
> -       clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 +
> -                       gmac_index),
> +       clrsetbits_le32((unsigned long)(socfpga_sysmgr_base +
> +                       SYSMGR_SOC64_EMAC0 + gmac_index),
>                         SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
>
>         return 0;
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> index bdc0f3ee6e..938999043e 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -56,29 +56,29 @@ void socfpga_bridges_reset(int enable)
>  {
>         if (enable) {
>                 /* clear idle request to all bridges */
> -               setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR,
> +               setbits_le32(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_CLR,
>                              ~0);
>
>                 /* Release all bridges from reset state */
>                 clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0);
>
>                 /* Poll until all idleack to 0 */
> -               while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
> +               while (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK))
>                         ;
>         } else {
>                 /* set idle request to all bridges */
> -               writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET);
> +               writel(~0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_SET);
>
>                 /* Enable the NOC timeout */
> -               writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> +               writel(1, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT);
>
>                 /* Poll until all idleack to 1 */
> -               while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^
> +               while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK) ^
>                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
>                         ;
>
>                 /* Poll until all idlestatus to 1 */
> -               while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^
> +               while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLESTATUS) ^
>                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
>                         ;
>
> @@ -88,7 +88,7 @@ void socfpga_bridges_reset(int enable)
>                                RSTMGR_BRGMODRST_FPGA2SOC_MASK));
>
>                 /* Disable NOC timeout */
> -               writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> +               writel(0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT);
>         }
>  }
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index cdfbd06327..fabedba6d1 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -53,7 +53,7 @@ void board_init_f(ulong dummy)
>  #ifdef CONFIG_HW_WATCHDOG
>         /* Ensure watchdog is paused when debugging is happening */
>         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
> -              socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
> +              socfpga_sysmgr_base + SYSMGR_SOC64_WDDBG);
>
>         /* Enable watchdog before initializing the HW */
>         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
> index c046bb17c9..0da9431517 100644
> --- a/arch/arm/mach-socfpga/system_manager_s10.c
> +++ b/arch/arm/mach-socfpga/system_manager_s10.c
> @@ -29,31 +29,31 @@ void populate_sysmgr_fpgaintf_module(void)
>         u32 handoff_val = 0;
>
>         /* Enable the signal for those HPS peripherals that use FPGA. */
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NAND_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_NAND;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SDMMC_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM0_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM1_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> -       writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
> +       writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN2);
>
>         handoff_val = 0;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC1_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> -       if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
> +       if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC2_USEFPGA) ==
>             SYSMGR_FPGAINTF_USEFPGA)
>                 handoff_val |= SYSMGR_FPGAINTF_EMAC2;
> -       writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
> +       writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN3);
>  }
>
>  /*
> @@ -69,7 +69,7 @@ void populate_sysmgr_pinmux(void)
>         for (i = 0; i < len; i = i + 2) {
>                 writel(sys_mgr_table_u32[i + 1],
>                        sys_mgr_table_u32[i] +
> -                      (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
> +                      (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_PINSEL0);
>         }
>
>         /* setup the pin ctrl */
> @@ -77,7 +77,7 @@ void populate_sysmgr_pinmux(void)
>         for (i = 0; i < len; i = i + 2) {
>                 writel(sys_mgr_table_u32[i + 1],
>                        sys_mgr_table_u32[i] +
> -                      (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
> +                      (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IOCTRL0);
>         }
>
>         /* setup the fpga use */
> @@ -85,7 +85,7 @@ void populate_sysmgr_pinmux(void)
>         for (i = 0; i < len; i = i + 2) {
>                 writel(sys_mgr_table_u32[i + 1],
>                        sys_mgr_table_u32[i] +
> -                      (u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA);
> +                      (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA);
>         }
>
>         /* setup the IO delay */
> @@ -93,6 +93,6 @@ void populate_sysmgr_pinmux(void)
>         for (i = 0; i < len; i = i + 2) {
>                 writel(sys_mgr_table_u32[i + 1],
>                        sys_mgr_table_u32[i] +
> -                      (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
> +                      (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IODELAY0);
>         }
>  }
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> index c9570fea38..b002f38215 100644
> --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> @@ -35,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void)
>  #ifdef CONFIG_SPL_BUILD
>         u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
>
> -       writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> +       writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
>  #endif
> -       return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> +       return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
>  }
>
>  const unsigned int cm_get_intosc_clk_hz(void)
> @@ -50,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void)
>  #ifdef CONFIG_SPL_BUILD
>         u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
>
> -       writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> +       writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
>  #endif
> -       return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> +       return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
>  }
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index 8948c31f45..9578aa743d 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -148,7 +148,7 @@ static int emif_reset(struct altera_sdram_platdata *plat)
>  static int poll_hmc_clock_status(void)
>  {
>         return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> -                                SYSMGR_S10_HMC_CLK),
> +                                SYSMGR_SOC64_HMC_CLK),
>                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
>  }
>
> --
> 2.19.0
>


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