[U-Boot] [PATCH v4 11/17] arm: agilex: Add clock handoff offset for Agilex

[Simon Goldschmidt]

On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>

> ---
>  arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++++++--
>  arch/arm/mach-socfpga/wrap_pll_config_s10.c      | 5 +++--
>  2 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
> index ba0f1fd1b2..abf04d9b04 100644
> --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
> @@ -26,8 +26,13 @@
>  #define S10_HANDOFF_OFFSET_LENGTH      0x4
>  #define S10_HANDOFF_OFFSET_DATA        0x10
>
> -#define S10_HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x608)
> -#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
> +#ifdef TARGET_SOCFPGA_STRATIX10
> +#define HANDOFF_CLOCK_OSC      (S10_HANDOFF_BASE + 0x608)
> +#define HANDOFF_CLOCK_FPGA     (S10_HANDOFF_BASE + 0x60C)
> +#else
> +#define HANDOFF_CLOCK_OSC      (S10_HANDOFF_BASE + 0x5fc)
> +#define HANDOFF_CLOCK_FPGA     (S10_HANDOFF_BASE + 0x600)
> +#endif
>
>  #define S10_HANDOFF_SIZE       4096
>
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> index b002f38215..d27accab57 100644
> --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> @@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void)
>  const unsigned int cm_get_osc_clk_hz(void)
>  {
>  #ifdef CONFIG_SPL_BUILD
> -       u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
> +
> +       u32 clock = readl(HANDOFF_CLOCK_OSC);
>
>         writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
>  #endif
> @@ -48,7 +49,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
>  const unsigned int cm_get_fpga_clk_hz(void)
>  {
>  #ifdef CONFIG_SPL_BUILD
> -       u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
> +       u32 clock = readl(HANDOFF_CLOCK_FPGA);
>
>         writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
>  #endif
> --
> 2.19.0
>