[U-Boot] [PATCH] imx: update i.MX8MQ clocks

Patrick Wildt patrick at blueri.se
Thu Oct 3 13:48:27 UTC 2019


I would like to add support for additional drivers, and for that
it makes sense to update the clock headers first, before adding
a node to the device tree.  Since no drivers use them so far it's
easy to just update the header and adjust the device tree.

Signed-off-by: Patrick Wildt <patrick at blueri.se>

diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
index 814a1b7df4..c35c23e293 100644
--- a/arch/arm/dts/fsl-imx8mq.dtsi
+++ b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -228,11 +228,11 @@
 	lcdif: lcdif at 30320000 {
 		compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 		reg = <0x0 0x30320000 0x0 0x10000>;
-		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
+		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
 			 <&clk IMX8MQ_CLK_DUMMY>,
 			 <&clk IMX8MQ_CLK_DUMMY>;
 		clock-names = "pix", "axi", "disp_axi";
-		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
+		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 		assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 		assigned-clock-rate = <594000000>;
 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -283,10 +283,10 @@
 		reg = <0x0 0x30b40000 0x0 0x10000>;
 		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clk IMX8MQ_CLK_DUMMY>,
-			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+			<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 			<&clk IMX8MQ_CLK_USDHC1_ROOT>;
 		clock-names = "ipg", "ahb", "per";
-		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 		assigned-clock-rates = <400000000>;
 		fsl,tuning-start-tap = <20>;
 		fsl,tuning-step= <2>;
@@ -299,7 +299,7 @@
 		reg = <0x0 0x30b50000 0x0 0x10000>;
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clk IMX8MQ_CLK_DUMMY>,
-			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+			<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 			<&clk IMX8MQ_CLK_USDHC2_ROOT>;
 		clock-names = "ipg", "ahb", "per";
 		fsl,tuning-start-tap = <20>;
@@ -316,19 +316,18 @@
 			<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 			<&clk IMX8MQ_CLK_ENET1_ROOT>,
-			<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
-			<&clk IMX8MQ_CLK_ENET_REF_DIV>,
-			<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+			<&clk IMX8MQ_CLK_ENET_TIMER>,
+			<&clk IMX8MQ_CLK_ENET_REF>,
+			<&clk IMX8MQ_CLK_ENET_PHY_REF>;
 		clock-names = "ipg", "ahb", "ptp",
 			"enet_clk_ref", "enet_out";
-		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
-				  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
+		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
+				  <&clk IMX8MQ_CLK_ENET_TIMER>,
+				  <&clk IMX8MQ_CLK_ENET_REF>;
 		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
 					 <&clk IMX8MQ_SYS2_PLL_100M>,
 					 <&clk IMX8MQ_SYS2_PLL_125M>;
-		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+		assigned-clock-rates = <0>, <100000000>, <125000000>;
 		stop-mode = <&gpr 0x10 3>;
 		fsl,num-tx-queues=<3>;
 		fsl,num-rx-queues=<3>;
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 11dcafcfde..65463673d2 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -1,10 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
@@ -148,465 +145,263 @@
 
 /* BUS TYPE */
 /* MAIN AXI */
-#define IMX8MQ_CLK_MAIN_AXI_SRC		103
-#define IMX8MQ_CLK_MAIN_AXI_CG		104
-#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV	105
-#define IMX8MQ_CLK_MAIN_AXI_DIV		106
+#define IMX8MQ_CLK_MAIN_AXI		103
 /* ENET AXI */
-#define IMX8MQ_CLK_ENET_AXI_SRC		107
-#define IMX8MQ_CLK_ENET_AXI_CG		108
-#define IMX8MQ_CLK_ENET_AXI_PRE_DIV	109
-#define IMX8MQ_CLK_ENET_AXI_DIV		110
+#define IMX8MQ_CLK_ENET_AXI		104
 /* NAND_USDHC_BUS */
-#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC		111
-#define IMX8MQ_CLK_NAND_USDHC_BUS_CG		112
-#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV	113
-#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV		114
+#define IMX8MQ_CLK_NAND_USDHC_BUS	105
 /* VPU BUS */
-#define IMX8MQ_CLK_VPU_BUS_SRC			115
-#define IMX8MQ_CLK_VPU_BUS_CG			116
-#define IMX8MQ_CLK_VPU_BUS_PRE_DIV		117
-#define IMX8MQ_CLK_VPU_BUS_DIV			118
+#define IMX8MQ_CLK_VPU_BUS		106
 /* DISP_AXI */
-#define IMX8MQ_CLK_DISP_AXI_SRC			119
-#define IMX8MQ_CLK_DISP_AXI_CG			120
-#define IMX8MQ_CLK_DISP_AXI_PRE_DIV		121
-#define IMX8MQ_CLK_DISP_AXI_DIV			122
+#define IMX8MQ_CLK_DISP_AXI		107
 /* DISP APB */
-#define IMX8MQ_CLK_DISP_APB_SRC			123
-#define IMX8MQ_CLK_DISP_APB_CG			124
-#define IMX8MQ_CLK_DISP_APB_PRE_DIV		125
-#define IMX8MQ_CLK_DISP_APB_DIV			126
+#define IMX8MQ_CLK_DISP_APB		108
 /* DISP RTRM */
-#define IMX8MQ_CLK_DISP_RTRM_SRC		127
-#define IMX8MQ_CLK_DISP_RTRM_CG			128
-#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV		129
-#define IMX8MQ_CLK_DISP_RTRM_DIV		130
+#define IMX8MQ_CLK_DISP_RTRM		109
 /* USB_BUS */
-#define IMX8MQ_CLK_USB_BUS_SRC			131
-#define IMX8MQ_CLK_USB_BUS_CG			132
-#define IMX8MQ_CLK_USB_BUS_PRE_DIV		133
-#define IMX8MQ_CLK_USB_BUS_DIV			134
+#define IMX8MQ_CLK_USB_BUS		110
 /* GPU_AXI */
-#define IMX8MQ_CLK_GPU_AXI_SRC			135
-#define IMX8MQ_CLK_GPU_AXI_CG			136
-#define IMX8MQ_CLK_GPU_AXI_PRE_DIV		137
-#define IMX8MQ_CLK_GPU_AXI_DIV			138
+#define IMX8MQ_CLK_GPU_AXI		111
 /* GPU_AHB */
-#define IMX8MQ_CLK_GPU_AHB_SRC			139
-#define IMX8MQ_CLK_GPU_AHB_CG			140
-#define IMX8MQ_CLK_GPU_AHB_PRE_DIV		141
-#define IMX8MQ_CLK_GPU_AHB_DIV			142
+#define IMX8MQ_CLK_GPU_AHB		112
 /* NOC */
-#define IMX8MQ_CLK_NOC_SRC			143
-#define IMX8MQ_CLK_NOC_CG			144
-#define IMX8MQ_CLK_NOC_PRE_DIV			145
-#define IMX8MQ_CLK_NOC_DIV			146
+#define IMX8MQ_CLK_NOC			113
 /* NOC_APB */
-#define IMX8MQ_CLK_NOC_APB_SRC			147
-#define IMX8MQ_CLK_NOC_APB_CG			148
-#define IMX8MQ_CLK_NOC_APB_PRE_DIV		149
-#define IMX8MQ_CLK_NOC_APB_DIV			150
+#define IMX8MQ_CLK_NOC_APB		115
 
 /* AHB */
-#define IMX8MQ_CLK_AHB_SRC			151
-#define IMX8MQ_CLK_AHB_CG			152
-#define IMX8MQ_CLK_AHB_PRE_DIV			153
-#define IMX8MQ_CLK_AHB_DIV			154
+#define IMX8MQ_CLK_AHB			116
 /* AUDIO AHB */
-#define IMX8MQ_CLK_AUDIO_AHB_SRC		155
-#define IMX8MQ_CLK_AUDIO_AHB_CG			156
-#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV		157
-#define IMX8MQ_CLK_AUDIO_AHB_DIV		158
+#define IMX8MQ_CLK_AUDIO_AHB		117
 
 /* DRAM_ALT */
-#define IMX8MQ_CLK_DRAM_ALT_SRC			159
-#define IMX8MQ_CLK_DRAM_ALT_CG			160
-#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV		161
-#define IMX8MQ_CLK_DRAM_ALT_DIV			162
+#define IMX8MQ_CLK_DRAM_ALT		118
 /* DRAM APB */
-#define IMX8MQ_CLK_DRAM_APB_SRC			163
-#define IMX8MQ_CLK_DRAM_APB_CG			164
-#define IMX8MQ_CLK_DRAM_APB_PRE_DIV		165
-#define IMX8MQ_CLK_DRAM_APB_DIV			166
+#define IMX8MQ_CLK_DRAM_APB		119
 /* VPU_G1 */
-#define IMX8MQ_CLK_VPU_G1_SRC			167
-#define IMX8MQ_CLK_VPU_G1_CG			168
-#define IMX8MQ_CLK_VPU_G1_PRE_DIV		169
-#define IMX8MQ_CLK_VPU_G1_DIV			170
+#define IMX8MQ_CLK_VPU_G1		120
 /* VPU_G2 */
-#define IMX8MQ_CLK_VPU_G2_SRC			171
-#define IMX8MQ_CLK_VPU_G2_CG			172
-#define IMX8MQ_CLK_VPU_G2_PRE_DIV		173
-#define IMX8MQ_CLK_VPU_G2_DIV			174
+#define IMX8MQ_CLK_VPU_G2		121
 /* DISP_DTRC */
-#define IMX8MQ_CLK_DISP_DTRC_SRC		175
-#define IMX8MQ_CLK_DISP_DTRC_CG			176
-#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV		177
-#define IMX8MQ_CLK_DISP_DTRC_DIV		178
+#define IMX8MQ_CLK_DISP_DTRC		122
 /* DISP_DC8000 */
-#define IMX8MQ_CLK_DISP_DC8000_SRC		179
-#define IMX8MQ_CLK_DISP_DC8000_CG		180
-#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV		181
-#define IMX8MQ_CLK_DISP_DC8000_DIV		182
+#define IMX8MQ_CLK_DISP_DC8000		123
 /* PCIE_CTRL */
-#define IMX8MQ_CLK_PCIE1_CTRL_SRC		183
-#define IMX8MQ_CLK_PCIE1_CTRL_CG		184
-#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV		185
-#define IMX8MQ_CLK_PCIE1_CTRL_DIV		186
+#define IMX8MQ_CLK_PCIE1_CTRL		124
 /* PCIE_PHY */
-#define IMX8MQ_CLK_PCIE1_PHY_SRC		187
-#define IMX8MQ_CLK_PCIE1_PHY_CG			188
-#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV		189
-#define IMX8MQ_CLK_PCIE1_PHY_DIV		190
+#define IMX8MQ_CLK_PCIE1_PHY		125
 /* PCIE_AUX */
-#define IMX8MQ_CLK_PCIE1_AUX_SRC		191
-#define IMX8MQ_CLK_PCIE1_AUX_CG			192
-#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV		193
-#define IMX8MQ_CLK_PCIE1_AUX_DIV		194
+#define IMX8MQ_CLK_PCIE1_AUX		126
 /* DC_PIXEL */
-#define IMX8MQ_CLK_DC_PIXEL_SRC			195
-#define IMX8MQ_CLK_DC_PIXEL_CG			196
-#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV		197
-#define IMX8MQ_CLK_DC_PIXEL_DIV			198
+#define IMX8MQ_CLK_DC_PIXEL		127
 /* LCDIF_PIXEL */
-#define IMX8MQ_CLK_LCDIF_PIXEL_SRC		199
-#define IMX8MQ_CLK_LCDIF_PIXEL_CG		200
-#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV		201
-#define IMX8MQ_CLK_LCDIF_PIXEL_DIV		202
+#define IMX8MQ_CLK_LCDIF_PIXEL		128
 /* SAI1~6 */
-#define IMX8MQ_CLK_SAI1_SRC			203
-#define IMX8MQ_CLK_SAI1_CG			204
-#define IMX8MQ_CLK_SAI1_PRE_DIV			205
-#define IMX8MQ_CLK_SAI1_DIV			206
-
-#define IMX8MQ_CLK_SAI2_SRC			207
-#define IMX8MQ_CLK_SAI2_CG			208
-#define IMX8MQ_CLK_SAI2_PRE_DIV			209
-#define IMX8MQ_CLK_SAI2_DIV			210
-
-#define IMX8MQ_CLK_SAI3_SRC			211
-#define IMX8MQ_CLK_SAI3_CG			212
-#define IMX8MQ_CLK_SAI3_PRE_DIV			213
-#define IMX8MQ_CLK_SAI3_DIV			214
-
-#define IMX8MQ_CLK_SAI4_SRC			215
-#define IMX8MQ_CLK_SAI4_CG			216
-#define IMX8MQ_CLK_SAI4_PRE_DIV			217
-#define IMX8MQ_CLK_SAI4_DIV			218
-
-#define IMX8MQ_CLK_SAI5_SRC			219
-#define IMX8MQ_CLK_SAI5_CG			220
-#define IMX8MQ_CLK_SAI5_PRE_DIV			221
-#define IMX8MQ_CLK_SAI5_DIV			222
-
-#define IMX8MQ_CLK_SAI6_SRC			223
-#define IMX8MQ_CLK_SAI6_CG			224
-#define IMX8MQ_CLK_SAI6_PRE_DIV			225
-#define IMX8MQ_CLK_SAI6_DIV			226
+#define IMX8MQ_CLK_SAI1			129
+
+#define IMX8MQ_CLK_SAI2			130
+
+#define IMX8MQ_CLK_SAI3			131
+
+#define IMX8MQ_CLK_SAI4			132
+
+#define IMX8MQ_CLK_SAI5			133
+
+#define IMX8MQ_CLK_SAI6			134
 /* SPDIF1 */
-#define IMX8MQ_CLK_SPDIF1_SRC			227
-#define IMX8MQ_CLK_SPDIF1_CG			228
-#define IMX8MQ_CLK_SPDIF1_PRE_DIV		229
-#define IMX8MQ_CLK_SPDIF1_DIV			230
+#define IMX8MQ_CLK_SPDIF1		135
 /* SPDIF2 */
-#define IMX8MQ_CLK_SPDIF2_SRC			231
-#define IMX8MQ_CLK_SPDIF2_CG			232
-#define IMX8MQ_CLK_SPDIF2_PRE_DIV		233
-#define IMX8MQ_CLK_SPDIF2_DIV			234
+#define IMX8MQ_CLK_SPDIF2		136
 /* ENET_REF */
-#define IMX8MQ_CLK_ENET_REF_SRC			235
-#define IMX8MQ_CLK_ENET_REF_CG			236
-#define IMX8MQ_CLK_ENET_REF_PRE_DIV		237
-#define IMX8MQ_CLK_ENET_REF_DIV			238
+#define IMX8MQ_CLK_ENET_REF		137
 /* ENET_TIMER */
-#define IMX8MQ_CLK_ENET_TIMER_SRC		239
-#define IMX8MQ_CLK_ENET_TIMER_CG		240
-#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV		241
-#define IMX8MQ_CLK_ENET_TIMER_DIV		242
+#define IMX8MQ_CLK_ENET_TIMER		138
 /* ENET_PHY */
-#define IMX8MQ_CLK_ENET_PHY_REF_SRC		243
-#define IMX8MQ_CLK_ENET_PHY_REF_CG		244
-#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV		245
-#define IMX8MQ_CLK_ENET_PHY_REF_DIV		246
+#define IMX8MQ_CLK_ENET_PHY_REF		139
 /* NAND */
-#define IMX8MQ_CLK_NAND_SRC			247
-#define IMX8MQ_CLK_NAND_CG			248
-#define IMX8MQ_CLK_NAND_PRE_DIV			249
-#define IMX8MQ_CLK_NAND_DIV			250
+#define IMX8MQ_CLK_NAND			140
 /* QSPI */
-#define IMX8MQ_CLK_QSPI_SRC			251
-#define IMX8MQ_CLK_QSPI_CG			252
-#define IMX8MQ_CLK_QSPI_PRE_DIV			253
-#define IMX8MQ_CLK_QSPI_DIV			254
+#define IMX8MQ_CLK_QSPI			141
 /* USDHC1 */
-#define IMX8MQ_CLK_USDHC1_SRC			255
-#define IMX8MQ_CLK_USDHC1_CG			256
-#define IMX8MQ_CLK_USDHC1_PRE_DIV		257
-#define IMX8MQ_CLK_USDHC1_DIV			258
+#define IMX8MQ_CLK_USDHC1		142
 /* USDHC2 */
-#define IMX8MQ_CLK_USDHC2_SRC			259
-#define IMX8MQ_CLK_USDHC2_CG			260
-#define IMX8MQ_CLK_USDHC2_PRE_DIV		261
-#define IMX8MQ_CLK_USDHC2_DIV			262
+#define IMX8MQ_CLK_USDHC2		143
 /* I2C1 */
-#define IMX8MQ_CLK_I2C1_SRC			263
-#define IMX8MQ_CLK_I2C1_CG			264
-#define IMX8MQ_CLK_I2C1_PRE_DIV			265
-#define IMX8MQ_CLK_I2C1_DIV			266
+#define IMX8MQ_CLK_I2C1			144
 /* I2C2 */
-#define IMX8MQ_CLK_I2C2_SRC			267
-#define IMX8MQ_CLK_I2C2_CG			268
-#define IMX8MQ_CLK_I2C2_PRE_DIV			269
-#define IMX8MQ_CLK_I2C2_DIV			270
+#define IMX8MQ_CLK_I2C2			145
 /* I2C3 */
-#define IMX8MQ_CLK_I2C3_SRC			271
-#define IMX8MQ_CLK_I2C3_CG			272
-#define IMX8MQ_CLK_I2C3_PRE_DIV			273
-#define IMX8MQ_CLK_I2C3_DIV			274
+#define IMX8MQ_CLK_I2C3			146
 /* I2C4 */
-#define IMX8MQ_CLK_I2C4_SRC			275
-#define IMX8MQ_CLK_I2C4_CG			276
-#define IMX8MQ_CLK_I2C4_PRE_DIV			277
-#define IMX8MQ_CLK_I2C4_DIV			278
+#define IMX8MQ_CLK_I2C4			147
 /* UART1 */
-#define IMX8MQ_CLK_UART1_SRC			279
-#define IMX8MQ_CLK_UART1_CG			280
-#define IMX8MQ_CLK_UART1_PRE_DIV		281
-#define IMX8MQ_CLK_UART1_DIV			282
+#define IMX8MQ_CLK_UART1		148
 /* UART2 */
-#define IMX8MQ_CLK_UART2_SRC			283
-#define IMX8MQ_CLK_UART2_CG			284
-#define IMX8MQ_CLK_UART2_PRE_DIV		285
-#define IMX8MQ_CLK_UART2_DIV			286
+#define IMX8MQ_CLK_UART2		149
 /* UART3 */
-#define IMX8MQ_CLK_UART3_SRC			287
-#define IMX8MQ_CLK_UART3_CG			288
-#define IMX8MQ_CLK_UART3_PRE_DIV		289
-#define IMX8MQ_CLK_UART3_DIV			290
+#define IMX8MQ_CLK_UART3		150
 /* UART4 */
-#define IMX8MQ_CLK_UART4_SRC			291
-#define IMX8MQ_CLK_UART4_CG			292
-#define IMX8MQ_CLK_UART4_PRE_DIV		293
-#define IMX8MQ_CLK_UART4_DIV			294
+#define IMX8MQ_CLK_UART4		151
 /* USB_CORE_REF */
-#define IMX8MQ_CLK_USB_CORE_REF_SRC		295
-#define IMX8MQ_CLK_USB_CORE_REF_CG		296
-#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV		297
-#define IMX8MQ_CLK_USB_CORE_REF_DIV		298
+#define IMX8MQ_CLK_USB_CORE_REF		152
 /* USB_PHY_REF */
-#define IMX8MQ_CLK_USB_PHY_REF_SRC		299
-#define IMX8MQ_CLK_USB_PHY_REF_CG		300
-#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV		301
-#define IMX8MQ_CLK_USB_PHY_REF_DIV		302
+#define IMX8MQ_CLK_USB_PHY_REF		153
 /* ECSPI1 */
-#define IMX8MQ_CLK_ECSPI1_SRC			303
-#define IMX8MQ_CLK_ECSPI1_CG			304
-#define IMX8MQ_CLK_ECSPI1_PRE_DIV		305
-#define IMX8MQ_CLK_ECSPI1_DIV			306
+#define IMX8MQ_CLK_ECSPI1		154
 /* ECSPI2 */
-#define IMX8MQ_CLK_ECSPI2_SRC			307
-#define IMX8MQ_CLK_ECSPI2_CG			308
-#define IMX8MQ_CLK_ECSPI2_PRE_DIV		309
-#define IMX8MQ_CLK_ECSPI2_DIV			310
+#define IMX8MQ_CLK_ECSPI2		155
 /* PWM1 */
-#define IMX8MQ_CLK_PWM1_SRC			311
-#define IMX8MQ_CLK_PWM1_CG			312
-#define IMX8MQ_CLK_PWM1_PRE_DIV			313
-#define IMX8MQ_CLK_PWM1_DIV			314
+#define IMX8MQ_CLK_PWM1			156
 /* PWM2 */
-#define IMX8MQ_CLK_PWM2_SRC			315
-#define IMX8MQ_CLK_PWM2_CG			316
-#define IMX8MQ_CLK_PWM2_PRE_DIV			317
-#define IMX8MQ_CLK_PWM2_DIV			318
+#define IMX8MQ_CLK_PWM2			157
 /* PWM3 */
-#define IMX8MQ_CLK_PWM3_SRC			319
-#define IMX8MQ_CLK_PWM3_CG			320
-#define IMX8MQ_CLK_PWM3_PRE_DIV			321
-#define IMX8MQ_CLK_PWM3_DIV			322
+#define IMX8MQ_CLK_PWM3			158
 /* PWM4 */
-#define IMX8MQ_CLK_PWM4_SRC			323
-#define IMX8MQ_CLK_PWM4_CG			324
-#define IMX8MQ_CLK_PWM4_PRE_DIV			325
-#define IMX8MQ_CLK_PWM4_DIV			326
+#define IMX8MQ_CLK_PWM4			159
 /* GPT1 */
-#define IMX8MQ_CLK_GPT1_SRC			327
-#define IMX8MQ_CLK_GPT1_CG			328
-#define IMX8MQ_CLK_GPT1_PRE_DIV			329
-#define IMX8MQ_CLK_GPT1_DIV			330
+#define IMX8MQ_CLK_GPT1			160
 /* WDOG */
-#define IMX8MQ_CLK_WDOG_SRC			331
-#define IMX8MQ_CLK_WDOG_CG			332
-#define IMX8MQ_CLK_WDOG_PRE_DIV			333
-#define IMX8MQ_CLK_WDOG_DIV			334
+#define IMX8MQ_CLK_WDOG			161
 /* WRCLK */
-#define IMX8MQ_CLK_WRCLK_SRC			335
-#define IMX8MQ_CLK_WRCLK_CG			336
-#define IMX8MQ_CLK_WRCLK_PRE_DIV		337
-#define IMX8MQ_CLK_WRCLK_DIV			338
+#define IMX8MQ_CLK_WRCLK		162
 /* DSI_CORE */
-#define IMX8MQ_CLK_DSI_CORE_SRC			339
-#define IMX8MQ_CLK_DSI_CORE_CG			340
-#define IMX8MQ_CLK_DSI_CORE_PRE_DIV		341
-#define IMX8MQ_CLK_DSI_CORE_DIV			342
+#define IMX8MQ_CLK_DSI_CORE		163
 /* DSI_PHY */
-#define IMX8MQ_CLK_DSI_PHY_REF_SRC		343
-#define IMX8MQ_CLK_DSI_PHY_REF_CG		344
-#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV		345
-#define IMX8MQ_CLK_DSI_PHY_REF_DIV		346
+#define IMX8MQ_CLK_DSI_PHY_REF		164
 /* DSI_DBI */
-#define IMX8MQ_CLK_DSI_DBI_SRC			347
-#define IMX8MQ_CLK_DSI_DBI_CG			348
-#define IMX8MQ_CLK_DSI_DBI_PRE_DIV		349
-#define IMX8MQ_CLK_DSI_DBI_DIV			350
+#define IMX8MQ_CLK_DSI_DBI		165
 /*DSI_ESC */
-#define IMX8MQ_CLK_DSI_ESC_SRC			351
-#define IMX8MQ_CLK_DSI_ESC_CG			352
-#define IMX8MQ_CLK_DSI_ESC_PRE_DIV		353
-#define IMX8MQ_CLK_DSI_ESC_DIV			354
+#define IMX8MQ_CLK_DSI_ESC		166
 /* CSI1_CORE */
-#define IMX8MQ_CLK_CSI1_CORE_SRC		355
-#define IMX8MQ_CLK_CSI1_CORE_CG			356
-#define  IMX8MQ_CLK_CSI1_CORE_PRE_DIV		357
-#define IMX8MQ_CLK_CSI1_CORE_DIV		358
+#define IMX8MQ_CLK_CSI1_CORE		167
 /* CSI1_PHY */
-#define IMX8MQ_CLK_CSI1_PHY_REF_SRC		359
-#define IMX8MQ_CLK_CSI1_PHY_REF_CG		360
-#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV		361
-#define IMX8MQ_CLK_CSI1_PHY_REF_DIV		362
+#define IMX8MQ_CLK_CSI1_PHY_REF		168
 /* CSI_ESC */
-#define IMX8MQ_CLK_CSI1_ESC_SRC			363
-#define IMX8MQ_CLK_CSI1_ESC_CG			364
-#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV		365
-#define IMX8MQ_CLK_CSI1_ESC_DIV			366
+#define IMX8MQ_CLK_CSI1_ESC		169
 /* CSI2_CORE */
-#define IMX8MQ_CLK_CSI2_CORE_SRC		367
-#define IMX8MQ_CLK_CSI2_CORE_CG			368
-#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV		369
-#define IMX8MQ_CLK_CSI2_CORE_DIV		370
+#define IMX8MQ_CLK_CSI2_CORE		170
 /* CSI2_PHY */
-#define IMX8MQ_CLK_CSI2_PHY_REF_SRC		371
-#define IMX8MQ_CLK_CSI2_PHY_REF_CG		372
-#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV		373
-#define IMX8MQ_CLK_CSI2_PHY_REF_DIV		374
+#define IMX8MQ_CLK_CSI2_PHY_REF		171
 /* CSI2_ESC */
-#define IMX8MQ_CLK_CSI2_ESC_SRC			375
-#define IMX8MQ_CLK_CSI2_ESC_CG			376
-#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV		377
-#define IMX8MQ_CLK_CSI2_ESC_DIV			378
+#define IMX8MQ_CLK_CSI2_ESC		172
 /* PCIE2_CTRL */
-#define IMX8MQ_CLK_PCIE2_CTRL_SRC		379
-#define IMX8MQ_CLK_PCIE2_CTRL_CG		380
-#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV		381
-#define IMX8MQ_CLK_PCIE2_CTRL_DIV		382
+#define IMX8MQ_CLK_PCIE2_CTRL		173
 /* PCIE2_PHY */
-#define IMX8MQ_CLK_PCIE2_PHY_SRC		383
-#define IMX8MQ_CLK_PCIE2_PHY_CG			384
-#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV		385
-#define IMX8MQ_CLK_PCIE2_PHY_DIV		386
+#define IMX8MQ_CLK_PCIE2_PHY		174
 /* PCIE2_AUX */
-#define IMX8MQ_CLK_PCIE2_AUX_SRC		387
-#define IMX8MQ_CLK_PCIE2_AUX_CG			388
-#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV		389
-#define IMX8MQ_CLK_PCIE2_AUX_DIV		390
+#define IMX8MQ_CLK_PCIE2_AUX		175
 /* ECSPI3 */
-#define IMX8MQ_CLK_ECSPI3_SRC			391
-#define IMX8MQ_CLK_ECSPI3_CG			392
-#define IMX8MQ_CLK_ECSPI3_PRE_DIV		393
-#define IMX8MQ_CLK_ECSPI3_DIV			394
+#define IMX8MQ_CLK_ECSPI3		176
 
 /* CCGR clocks */
-#define IMX8MQ_CLK_A53_ROOT			395
-#define IMX8MQ_CLK_DRAM_ROOT			396
-#define IMX8MQ_CLK_ECSPI1_ROOT			397
-#define IMX8MQ_CLK_ECSPI2_ROOT			398
-#define IMX8MQ_CLK_ECSPI3_ROOT			399
-#define IMX8MQ_CLK_ENET1_ROOT			400
-#define IMX8MQ_CLK_GPT1_ROOT			401
-#define IMX8MQ_CLK_I2C1_ROOT			402
-#define IMX8MQ_CLK_I2C2_ROOT			403
-#define IMX8MQ_CLK_I2C3_ROOT			404
-#define IMX8MQ_CLK_I2C4_ROOT			405
-#define IMX8MQ_CLK_M4_ROOT			406
-#define IMX8MQ_CLK_PCIE1_ROOT			407
-#define IMX8MQ_CLK_PCIE2_ROOT			408
-#define IMX8MQ_CLK_PWM1_ROOT			409
-#define IMX8MQ_CLK_PWM2_ROOT			410
-#define IMX8MQ_CLK_PWM3_ROOT			411
-#define IMX8MQ_CLK_PWM4_ROOT			412
-#define IMX8MQ_CLK_QSPI_ROOT			413
-#define IMX8MQ_CLK_SAI1_ROOT			414
-#define IMX8MQ_CLK_SAI2_ROOT			415
-#define IMX8MQ_CLK_SAI3_ROOT			416
-#define IMX8MQ_CLK_SAI4_ROOT			417
-#define IMX8MQ_CLK_SAI5_ROOT			418
-#define IMX8MQ_CLK_SAI6_ROOT			419
-#define IMX8MQ_CLK_UART1_ROOT			420
-#define IMX8MQ_CLK_UART2_ROOT			421
-#define IMX8MQ_CLK_UART3_ROOT			422
-#define IMX8MQ_CLK_UART4_ROOT			423
-#define IMX8MQ_CLK_USB1_CTRL_ROOT		424
-#define IMX8MQ_CLK_USB2_CTRL_ROOT		425
-#define IMX8MQ_CLK_USB1_PHY_ROOT		426
-#define IMX8MQ_CLK_USB2_PHY_ROOT		427
-#define IMX8MQ_CLK_USDHC1_ROOT			428
-#define IMX8MQ_CLK_USDHC2_ROOT			429
-#define IMX8MQ_CLK_WDOG1_ROOT			430
-#define IMX8MQ_CLK_WDOG2_ROOT			431
-#define IMX8MQ_CLK_WDOG3_ROOT			432
-#define IMX8MQ_CLK_GPU_ROOT			433
-#define IMX8MQ_CLK_HEVC_ROOT			434
-#define IMX8MQ_CLK_AVC_ROOT			435
-#define IMX8MQ_CLK_VP9_ROOT			436
-#define IMX8MQ_CLK_HEVC_INTER_ROOT		437
-#define IMX8MQ_CLK_DISP_ROOT			438
-#define IMX8MQ_CLK_HDMI_ROOT			439
-#define IMX8MQ_CLK_HDMI_PHY_ROOT		440
-#define IMX8MQ_CLK_VPU_DEC_ROOT			441
-#define IMX8MQ_CLK_CSI1_ROOT			442
-#define IMX8MQ_CLK_CSI2_ROOT			443
-#define IMX8MQ_CLK_RAWNAND_ROOT			444
-#define IMX8MQ_CLK_SDMA1_ROOT			445
-#define IMX8MQ_CLK_SDMA2_ROOT			446
-#define IMX8MQ_CLK_VPU_G1_ROOT			447
-#define IMX8MQ_CLK_VPU_G2_ROOT			448
+#define IMX8MQ_CLK_A53_ROOT			177
+#define IMX8MQ_CLK_DRAM_ROOT			178
+#define IMX8MQ_CLK_ECSPI1_ROOT			179
+#define IMX8MQ_CLK_ECSPI2_ROOT			180
+#define IMX8MQ_CLK_ECSPI3_ROOT			181
+#define IMX8MQ_CLK_ENET1_ROOT			182
+#define IMX8MQ_CLK_GPT1_ROOT			183
+#define IMX8MQ_CLK_I2C1_ROOT			184
+#define IMX8MQ_CLK_I2C2_ROOT			185
+#define IMX8MQ_CLK_I2C3_ROOT			186
+#define IMX8MQ_CLK_I2C4_ROOT			187
+#define IMX8MQ_CLK_M4_ROOT			188
+#define IMX8MQ_CLK_PCIE1_ROOT			189
+#define IMX8MQ_CLK_PCIE2_ROOT			190
+#define IMX8MQ_CLK_PWM1_ROOT			191
+#define IMX8MQ_CLK_PWM2_ROOT			192
+#define IMX8MQ_CLK_PWM3_ROOT			193
+#define IMX8MQ_CLK_PWM4_ROOT			194
+#define IMX8MQ_CLK_QSPI_ROOT			195
+#define IMX8MQ_CLK_SAI1_ROOT			196
+#define IMX8MQ_CLK_SAI2_ROOT			197
+#define IMX8MQ_CLK_SAI3_ROOT			198
+#define IMX8MQ_CLK_SAI4_ROOT			199
+#define IMX8MQ_CLK_SAI5_ROOT			200
+#define IMX8MQ_CLK_SAI6_ROOT			201
+#define IMX8MQ_CLK_UART1_ROOT			202
+#define IMX8MQ_CLK_UART2_ROOT			203
+#define IMX8MQ_CLK_UART3_ROOT			204
+#define IMX8MQ_CLK_UART4_ROOT			205
+#define IMX8MQ_CLK_USB1_CTRL_ROOT		206
+#define IMX8MQ_CLK_USB2_CTRL_ROOT		207
+#define IMX8MQ_CLK_USB1_PHY_ROOT		208
+#define IMX8MQ_CLK_USB2_PHY_ROOT		209
+#define IMX8MQ_CLK_USDHC1_ROOT			210
+#define IMX8MQ_CLK_USDHC2_ROOT			211
+#define IMX8MQ_CLK_WDOG1_ROOT			212
+#define IMX8MQ_CLK_WDOG2_ROOT			213
+#define IMX8MQ_CLK_WDOG3_ROOT			214
+#define IMX8MQ_CLK_GPU_ROOT			215
+#define IMX8MQ_CLK_HEVC_ROOT			216
+#define IMX8MQ_CLK_AVC_ROOT			217
+#define IMX8MQ_CLK_VP9_ROOT			218
+#define IMX8MQ_CLK_HEVC_INTER_ROOT		219
+#define IMX8MQ_CLK_DISP_ROOT			220
+#define IMX8MQ_CLK_HDMI_ROOT			221
+#define IMX8MQ_CLK_HDMI_PHY_ROOT		222
+#define IMX8MQ_CLK_VPU_DEC_ROOT			223
+#define IMX8MQ_CLK_CSI1_ROOT			224
+#define IMX8MQ_CLK_CSI2_ROOT			225
+#define IMX8MQ_CLK_RAWNAND_ROOT			226
+#define IMX8MQ_CLK_SDMA1_ROOT			227
+#define IMX8MQ_CLK_SDMA2_ROOT			228
+#define IMX8MQ_CLK_VPU_G1_ROOT			229
+#define IMX8MQ_CLK_VPU_G2_ROOT			230
 
 /* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT			449
-#define IMX8MQ_SYS2_PLL_OUT			450
-#define IMX8MQ_SYS3_PLL_OUT			451
-#define IMX8MQ_DRAM_PLL_OUT			452
-
-#define IMX8MQ_GPT_3M_CLK			453
-
-#define IMX8MQ_CLK_IPG_ROOT			454
-#define IMX8MQ_CLK_IPG_AUDIO_ROOT		455
-#define IMX8MQ_CLK_SAI1_IPG			456
-#define IMX8MQ_CLK_SAI2_IPG			457
-#define IMX8MQ_CLK_SAI3_IPG			458
-#define IMX8MQ_CLK_SAI4_IPG			459
-#define IMX8MQ_CLK_SAI5_IPG			460
-#define IMX8MQ_CLK_SAI6_IPG			461
+#define IMX8MQ_SYS1_PLL_OUT			231
+#define IMX8MQ_SYS2_PLL_OUT			232
+#define IMX8MQ_SYS3_PLL_OUT			233
+#define IMX8MQ_DRAM_PLL_OUT			234
+
+#define IMX8MQ_GPT_3M_CLK			235
+
+#define IMX8MQ_CLK_IPG_ROOT			236
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
+#define IMX8MQ_CLK_SAI1_IPG			238
+#define IMX8MQ_CLK_SAI2_IPG			239
+#define IMX8MQ_CLK_SAI3_IPG			240
+#define IMX8MQ_CLK_SAI4_IPG			241
+#define IMX8MQ_CLK_SAI5_IPG			242
+#define IMX8MQ_CLK_SAI6_IPG			243
 
 /* DSI AHB/IPG clocks */
 /* rxesc clock */
-#define IMX8MQ_CLK_DSI_AHB_SRC                  462
-#define IMX8MQ_CLK_DSI_AHB_CG                   463
-#define IMX8MQ_CLK_DSI_AHB_PRE_DIV              464
-#define IMX8MQ_CLK_DSI_AHB_DIV                  465
+#define IMX8MQ_CLK_DSI_AHB			244
 /* txesc clock */
-#define IMX8MQ_CLK_DSI_IPG_DIV                  466
-
-/* VIDEO2 PLL */
-#define IMX8MQ_VIDEO2_PLL1_REF_SEL		467
-#define IMX8MQ_VIDEO2_PLL1_REF_DIV		468
-#define IMX8MQ_VIDEO2_PLL1			469
-#define IMX8MQ_VIDEO2_PLL1_OUT			470
-#define IMX8MQ_VIDEO2_PLL1_OUT_DIV		471
-#define IMX8MQ_VIDEO2_PLL2			472
-#define IMX8MQ_VIDEO2_PLL2_DIV			473
-#define IMX8MQ_VIDEO2_PLL2_OUT			474
-#define IMX8MQ_CLK_TMU_ROOT			475
-
-#define IMX8MQ_CLK_END				476
+#define IMX8MQ_CLK_DSI_IPG_DIV                  245
+
+#define IMX8MQ_CLK_TMU_ROOT			246
+
+/* Display root clocks */
+#define IMX8MQ_CLK_DISP_AXI_ROOT		247
+#define IMX8MQ_CLK_DISP_APB_ROOT		248
+#define IMX8MQ_CLK_DISP_RTRM_ROOT		249
+
+#define IMX8MQ_CLK_OCOTP_ROOT			250
+
+#define IMX8MQ_CLK_DRAM_ALT_ROOT		251
+#define IMX8MQ_CLK_DRAM_CORE			252
+
+#define IMX8MQ_CLK_MU_ROOT			253
+#define IMX8MQ_VIDEO2_PLL_OUT			254
+
+#define IMX8MQ_CLK_CLKO2			255
+
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
+
+#define IMX8MQ_CLK_CLKO1			257
+#define IMX8MQ_CLK_ARM				258
+
+#define IMX8MQ_CLK_GPIO1_ROOT			259
+#define IMX8MQ_CLK_GPIO2_ROOT			260
+#define IMX8MQ_CLK_GPIO3_ROOT			261
+#define IMX8MQ_CLK_GPIO4_ROOT			262
+#define IMX8MQ_CLK_GPIO5_ROOT			263
+
+#define IMX8MQ_CLK_SNVS_ROOT			264
+#define IMX8MQ_CLK_GIC				265
+
+#define IMX8MQ_CLK_END				266
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */


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