[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

Marek Vasut marex at denx.de
Sun Oct 6 13:40:50 UTC 2019


On 10/6/19 1:25 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen <dalon.westergreen at intel.com>
>>> Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>>
>> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
>> thing, except more fine-grained ?
>>> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
>>> 0000000000..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
>>> common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
>>> * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+	
>>> #address-cells = <1>;+	#size-cells = <1>;++	chosen {+		tick
>>> -timer = &timer2;+		u-boot,dm-pre-reloc;+	};++	memory at 0 {+	
>>> 	u-boot,dm-pre-reloc;+	};++	soc {+		u-boot,dm-pre-
>>> reloc;++		clkmgr at ffd04000 {+			u-boot,dm-pre-
>>> reloc;++			clocks {+					u-
>>> boot,dm-pre-reloc;++					cb_intosc_hs_div
>>> 2_clk {+						u-boot,dm-pre-reloc;+	
>>> 				};++					cb_i
>>> ntosc_ls_clk {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	f2s_free_clk {+						u-boot,dm-
>>> pre-reloc;+					};++				
>>> 	osc1 {+						u-boot,dm-pre-
>>> reloc;+					};++				
>>> 	main_pll at 40 {+						u-boot,dm-
>>> pre-reloc;++						main_mpu_base_cl
>>> k {+							u-boot,dm-pre-
>>> reloc;+						};++			
>>> 			main_noc_base_clk {+					
>>> 		u-boot,dm-pre-reloc;+						
>>> };++						main_emaca_clk at 68 {+	
>>> 						u-boot,dm-pre-reloc;+		
>>> 				};
>>
>> Do we really need all this in SPL for every board ?
> 
> We likely don't, but we arent that memory constrained in a10 and this simplifies
> devicetree creation for custom boards.

We shouldn't enable what we don't need in SPL.

> We do have customers using ethernet
> in spl, for example.  I can slim this down, but is it necessary?

Just enable the necessary clock in the board-specific DT, since it's a
board-specific configuration.


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