[U-Boot] [PATCH 2/4] ram: k3-j721e: Add support for J721E DDR controller

Lokesh Vutla lokeshvutla at ti.com
Mon Oct 7 13:56:36 UTC 2019


From: Kevin Scholz <k-scholz at ti.com>

The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz at ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
 drivers/ram/Kconfig                           |   11 +
 drivers/ram/Makefile                          |    1 +
 drivers/ram/k3-j721e/Makefile                 |    8 +
 drivers/ram/k3-j721e/cps_drv_lpddr4.h         |  119 +
 drivers/ram/k3-j721e/k3-j721e-ddrss.c         |  372 +
 drivers/ram/k3-j721e/lpddr4.c                 | 2119 +++++
 .../k3-j721e/lpddr4_address_slice_0_macros.h  |  825 ++
 drivers/ram/k3-j721e/lpddr4_ctl_regs.h        | 1546 ++++
 .../ram/k3-j721e/lpddr4_data_slice_0_macros.h | 2373 +++++
 .../ram/k3-j721e/lpddr4_data_slice_1_macros.h | 2373 +++++
 .../ram/k3-j721e/lpddr4_data_slice_2_macros.h | 2373 +++++
 .../ram/k3-j721e/lpddr4_data_slice_3_macros.h | 2373 +++++
 .../k3-j721e/lpddr4_ddr_controller_macros.h   | 7793 +++++++++++++++++
 drivers/ram/k3-j721e/lpddr4_if.h              |  578 ++
 drivers/ram/k3-j721e/lpddr4_obj_if.c          |   55 +
 drivers/ram/k3-j721e/lpddr4_obj_if.h          |  383 +
 drivers/ram/k3-j721e/lpddr4_phy_core_macros.h | 2061 +++++
 drivers/ram/k3-j721e/lpddr4_pi_macros.h       | 5397 ++++++++++++
 drivers/ram/k3-j721e/lpddr4_private.h         |   56 +
 drivers/ram/k3-j721e/lpddr4_sanity.h          | 1165 +++
 drivers/ram/k3-j721e/lpddr4_structs_if.h      |  121 +
 21 files changed, 32102 insertions(+)
 create mode 100644 drivers/ram/k3-j721e/Makefile
 create mode 100644 drivers/ram/k3-j721e/cps_drv_lpddr4.h
 create mode 100644 drivers/ram/k3-j721e/k3-j721e-ddrss.c
 create mode 100644 drivers/ram/k3-j721e/lpddr4.c
 create mode 100644 drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_ctl_regs.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_if.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_obj_if.c
 create mode 100644 drivers/ram/k3-j721e/lpddr4_obj_if.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_pi_macros.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_private.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_sanity.h
 create mode 100644 drivers/ram/k3-j721e/lpddr4_structs_if.h

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 568d8f2c6a..bb431ccfbf 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,5 +54,16 @@ config K3_AM654_DDRSS
 	  config add support for the initialization of the external
 	  SDRAM devices connected to DDR subsystem.
 
+config K3_J721E_DDRSS
+	bool "Enable J721E DDRSS support"
+	depends on RAM
+	help
+	  The J721E DDR subsystem comprises DDR controller, DDR PHY and
+	  wrapper logic to integrate these blocks in the device. The DDR
+	  subsystem is used to provide an interface to external SDRAM
+	  devices which can be utilized for storing program or data.
+	  Enabling this config adds support for the DDR memory controller
+	  on J721E family of SoCs.
+
 source "drivers/ram/rockchip/Kconfig"
 source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 976ec66df7..4b77969b39 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 
 obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
 obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
diff --git a/drivers/ram/k3-j721e/Makefile b/drivers/ram/k3-j721e/Makefile
new file mode 100644
index 0000000000..d60cc626e0
--- /dev/null
+++ b/drivers/ram/k3-j721e/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+#
+
+obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
diff --git a/drivers/ram/k3-j721e/cps_drv_lpddr4.h b/drivers/ram/k3-j721e/cps_drv_lpddr4.h
new file mode 100644
index 0000000000..706a5cde01
--- /dev/null
+++ b/drivers/ram/k3-j721e/cps_drv_lpddr4.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/******************************************************************************
+ *
+ * Copyright (C) 2017-2018 Cadence Design Systems, Inc.
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * cps_drv_lpddr4.h
+ * Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
+ *****************************************************************************
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#include <stddef.h>
+#include <inttypes.h>
+#include <asm/io.h>
+
+/**
+ *  \brief    Read a 32-bit value from memory.
+ *  \param    reg   address of the memory mapped hardware register
+ *  \return   the value at the given address
+ */
+#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
+
+/**
+ *  \brief   Write a 32-bit address value to memory.
+ *  \param   reg     address of the memory mapped hardware register
+ *  \param   value   unsigned 32-bit value to write
+ */
+#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
+
+/**
+ *  \brief    Subtitue the value of fld macro and concatinate with required string
+ *  \param    fld         field name
+ */
+#define CPS_FLD_MASK(fld)  (fld ## _MASK)
+#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
+#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
+#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
+#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
+
+/**
+ *  \brief    Read a value of bit-field from the register value.
+ *  \param    reg         register name
+ *  \param    fld         field name
+ *  \param    reg_value   register value
+ *  \return   bit-field value
+ */
+#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)),  \
+						(uint32_t)(CPS_FLD_SHIFT(fld)), \
+						(uint32_t)(reg_value)))
+
+/**
+ *  \brief    Write a value of the bit-field into the register value.
+ *  \param    reg         register name
+ *  \param    fld         field name
+ *  \param    reg_value   register value
+ *  \param    value       value to be written to bit-field
+ *  \return   modified register value
+ */
+#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)),  \
+						(uint32_t)(CPS_FLD_SHIFT(fld)), \
+						(uint32_t)(reg_value), (uint32_t)(value)))
+
+/**
+ *  \brief    Set bit within the register value.
+ *  \param    reg         register name
+ *  \param    fld         field name
+ *  \param    reg_value   register value
+ *  \return   modified register value
+ */
+#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
+					(uint32_t)(CPS_FLD_MASK(fld)),  \
+					(uint32_t)(CPS_FLD_WOCLR(fld)), \
+					(uint32_t)(reg_value)))
+
+static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
+{
+	uint32_t result = (reg_value & mask) >> shift;
+
+	return (result);
+}
+
+/**
+ *  \brief    Write a value of the bit-field into the register value.
+ *  \param    mask        mask for the bit-field
+ *  \param    shift       bit-field shift from LSB
+ *  \param    reg_value   register value
+ *  \param    value       value to be written to bit-field
+ *  \return   modified register value
+ */
+static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
+{
+	uint32_t new_value = (value << shift) & mask;
+
+	new_value = (reg_value & ~mask) | new_value;
+	return (new_value);
+}
+
+/**
+ *  \brief    Set bit within the register value.
+ *  \param    width       width of the bit-field
+ *  \param    mask        mask for the bit-field
+ *  \param    is_woclr    is bit-field has 'write one to clear' flag set
+ *  \param    reg_value   register value
+ *  \return   modified register value
+ */
+static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
+{
+	uint32_t new_value = reg_value;
+	/* Confirm the field to be bit and not write to clear type */
+	if ((width == 1U) && (is_woclr == 0U)) {
+		new_value |= mask;
+	}
+
+	return (new_value);
+}
+#endif /* CPS_DRV_H_ */
diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
new file mode 100644
index 0000000000..9feb0aa766
--- /dev/null
+++ b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' J721E DDRSS driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <wait_bit.h>
+
+#include "lpddr4_obj_if.h"
+#include "lpddr4_if.h"
+#include "lpddr4_structs_if.h"
+#include "lpddr4_ctl_regs.h"
+
+#define SRAM_MAX 512
+
+#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
+#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
+
+struct j721e_ddrss_desc {
+	struct udevice *dev;
+	void __iomem *ddrss_ss_cfg;
+	void __iomem *ddrss_ctrl_mmr;
+	struct power_domain ddrcfg_pwrdmn;
+	struct power_domain ddrdata_pwrdmn;
+	struct clk ddr_clk;
+	struct clk osc_clk;
+	u32 ddr_freq1;
+	u32 ddr_freq2;
+	u32 ddr_fhs_cnt;
+};
+
+static LPDDR4_OBJ *driverdt;
+static lpddr4_config config;
+static lpddr4_privatedata pd;
+
+static struct j721e_ddrss_desc *ddrss;
+
+#define TH_MACRO_EXP(fld, str) (fld##str)
+
+#define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
+#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
+#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
+#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
+#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
+
+#define str(s) #s
+#define xstr(s) str(s)
+
+#define  CTL_SHIFT 11
+#define  PHY_SHIFT 11
+#define  PI_SHIFT 10
+
+#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
+	char *i, *pstr= xstr(REG); offset = 0;\
+	for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
+		offset = offset * 10 + (*i - '0'); }\
+	} while (0)
+
+static void j721e_lpddr4_ack_freq_upd_req(void)
+{
+	unsigned int req_type, counter;
+
+	debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+
+	for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
+		if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
+				      CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+				      true, 10000, false)) {
+			printf("Timeout during frequency handshake\n");
+			hang();
+		}
+
+		req_type = readl(ddrss->ddrss_ctrl_mmr +
+				 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+
+		debug("%s: received freq change req: req type = %d, req no. = %d \n",
+		      __func__, req_type, counter);
+
+		if (req_type == 1)
+			clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
+		else if (req_type == 2)
+			clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
+		else if (req_type == 0)
+			/* Put DDR pll in bypass mode */
+			clk_set_rate(&ddrss->ddr_clk,
+				     clk_get_rate(&ddrss->osc_clk));
+		else
+			printf("%s: Invalid freq request type\n", __func__);
+
+		writel(0x1, ddrss->ddrss_ctrl_mmr +
+		       CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+		if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
+				      CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+				      false, 10, false)) {
+			printf("Timeout during frequency handshake\n");
+			hang();
+		}
+		writel(0x0, ddrss->ddrss_ctrl_mmr +
+		       CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+	}
+}
+
+static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
+				      lpddr4_infotype infotype)
+{
+	if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
+		j721e_lpddr4_ack_freq_upd_req();
+	}
+}
+
+static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
+{
+	int ret;
+
+	debug("%s(ddrss=%p)\n", __func__, ddrss);
+
+	ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
+	if (ret) {
+		dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
+	if (ret) {
+		dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
+{
+	struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
+	phys_addr_t reg;
+	int ret;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	reg = dev_read_addr_name(dev, "cfg");
+	if (reg == FDT_ADDR_T_NONE) {
+		dev_err(dev, "No reg property for DDRSS wrapper logic\n");
+		return -EINVAL;
+	}
+	ddrss->ddrss_ss_cfg = (void *)reg;
+
+	reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
+	if (reg == FDT_ADDR_T_NONE) {
+		dev_err(dev, "No reg property for CTRL MMR\n");
+		return -EINVAL;
+	}
+	ddrss->ddrss_ctrl_mmr = (void *)reg;
+
+	ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
+	if (ret) {
+		dev_err(dev, "power_domain_get() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
+	if (ret) {
+		dev_err(dev, "power_domain_get() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
+	if (ret)
+		dev_err(dev, "clk get failed%d\n", ret);
+
+	ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
+	if (ret)
+		dev_err(dev, "clk get failed for osc clk %d\n", ret);
+
+	ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
+	if (ret)
+		dev_err(dev, "ddr freq1 not populated %d\n", ret);
+
+	ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
+	if (ret)
+		dev_err(dev, "ddr freq2 not populated %d\n", ret);
+
+	ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
+	if (ret)
+		dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
+
+	/* Put DDR pll in bypass mode */
+	ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
+	if (ret)
+		dev_err(dev, "ddr clk bypass failed\n");
+
+	return ret;
+}
+
+void j721e_lpddr4_probe(void)
+{
+	uint32_t status = 0U;
+	uint16_t configsize = 0U;
+
+	status = driverdt->probe(&config, &configsize);
+
+	if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
+	    || (configsize > SRAM_MAX)) {
+		printf("LPDDR4_Probe: FAIL\n");
+		hang();
+	} else {
+		debug("LPDDR4_Probe: PASS\n");
+	}
+}
+
+void j721e_lpddr4_init(void)
+{
+	uint32_t status = 0U;
+
+	if ((sizeof(pd) != sizeof(lpddr4_privatedata))
+	    || (sizeof(pd) > SRAM_MAX)) {
+		printf("LPDDR4_Init: FAIL\n");
+		hang();
+	}
+
+	config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
+	config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
+
+	status = driverdt->init(&pd, &config);
+
+	if ((status > 0U) ||
+	    (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
+	    (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
+	    (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
+		printf("LPDDR4_Init: FAIL\n");
+		hang();
+	} else {
+		debug("LPDDR4_Init: PASS\n");
+	}
+}
+
+void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
+{
+	int ret, i;
+
+	ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
+				 (u32 *) reginit_data->denalictlreg,
+				 LPDDR4_CTL_REG_COUNT);
+	if (ret)
+		printf("Error reading ctrl data\n");
+
+	for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
+		reginit_data->updatectlreg[i] = true;
+
+	ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
+				 (u32 *) reginit_data->denaliphyindepreg,
+				 LPDDR4_PHY_INDEP_REG_COUNT);
+	if (ret)
+		printf("Error reading PI data\n");
+
+	for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
+		reginit_data->updatephyindepreg[i] = true;
+
+	ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
+				 (u32 *) reginit_data->denaliphyreg,
+				 LPDDR4_PHY_REG_COUNT);
+	if (ret)
+		printf("Error reading PHY data\n");
+
+	for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
+		reginit_data->updatephyreg[i] = true;
+}
+
+void j721e_lpddr4_hardware_reg_init(void)
+{
+	uint32_t status = 0U;
+	lpddr4_reginitdata reginitdata;
+
+	populate_data_array_from_dt(&reginitdata);
+
+	status = driverdt->writectlconfig(&pd, &reginitdata);
+	if (!status) {
+		status = driverdt->writephyindepconfig(&pd, &reginitdata);
+	}
+	if (!status) {
+		status = driverdt->writephyconfig(&pd, &reginitdata);
+	}
+	if (status) {
+		printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
+		hang();
+	}
+
+	return;
+}
+
+void j721e_lpddr4_start(void)
+{
+	uint32_t status = 0U;
+	uint32_t regval = 0U;
+	uint32_t offset = 0U;
+
+	TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
+
+	status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
+	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
+		printf("LPDDR4_StartTest: FAIL\n");
+		hang();
+	}
+
+	status = driverdt->start(&pd);
+	if (status > 0U) {
+		printf("LPDDR4_StartTest: FAIL\n");
+		hang();
+	}
+
+	status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
+	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
+		printf("LPDDR4_Start: FAIL\n");
+		hang();
+	} else {
+		debug("LPDDR4_Start: PASS\n");
+	}
+}
+
+static int j721e_ddrss_probe(struct udevice *dev)
+{
+	int ret;
+	ddrss = dev_get_priv(dev);
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	ret = j721e_ddrss_ofdata_to_priv(dev);
+	if (ret)
+		return ret;
+
+	ddrss->dev = dev;
+	ret = j721e_ddrss_power_on(ddrss);
+	if (ret)
+		return ret;
+
+	driverdt = lpddr4_getinstance();
+	j721e_lpddr4_probe();
+	j721e_lpddr4_init();
+	j721e_lpddr4_hardware_reg_init();
+	j721e_lpddr4_start();
+
+	return ret;
+}
+
+static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
+{
+	return 0;
+}
+
+static struct ram_ops j721e_ddrss_ops = {
+	.get_info = j721e_ddrss_get_info,
+};
+
+static const struct udevice_id j721e_ddrss_ids[] = {
+	{.compatible = "ti,j721e-ddrss"},
+	{}
+};
+
+U_BOOT_DRIVER(j721e_ddrss) = {
+	.name = "j721e_ddrss",
+	.id = UCLASS_RAM,
+	.of_match = j721e_ddrss_ids,
+	.ops = &j721e_ddrss_ops,
+	.probe = j721e_ddrss_probe,
+	.priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
+};
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c
new file mode 100644
index 0000000000..2c3892d8d7
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4.c
@@ -0,0 +1,2119 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/******************************************************************************
+ * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * lpddr4.c
+ *
+ *****************************************************************************
+ */
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_if.h"
+#include "lpddr4_private.h"
+#include "lpddr4_sanity.h"
+#include "lpddr4_structs_if.h"
+
+#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
+
+/**
+ * Internal Function:Poll for status of interrupt received by the Controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] irqBit Interrupt status bit to be checked.
+ * @param[in] delay time delay.
+ * @return CDN_EOK on success (Interrupt status high).
+ * @return EIO on poll time out.
+ * @return EINVAL checking status was not successful.
+ */
+static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd,
+				  lpddr4_ctlinterrupt irqbit, uint32_t delay)
+{
+
+	uint32_t result = 0U;
+	uint32_t timeout = 0U;
+	bool irqstatus = false;
+
+	/* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
+	do {
+		if (++timeout == delay) {
+			result = EIO;
+			break;
+		}
+		/* cps_delayns(10000000U); */
+		result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
+	} while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
+
+	return result;
+}
+
+/**
+ * Internal Function:Poll for status of interrupt received by the PHY Independent Module.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] irqBit Interrupt status bit to be checked.
+ * @param[in] delay time delay.
+ * @return CDN_EOK on success (Interrupt status high).
+ * @return EIO on poll time out.
+ * @return EINVAL checking status was not successful.
+ */
+static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,
+				       lpddr4_phyindepinterrupt irqbit,
+				       uint32_t delay)
+{
+
+	uint32_t result = 0U;
+	uint32_t timeout = 0U;
+	bool irqstatus = false;
+
+	/* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
+	do {
+		if (++timeout == delay) {
+			result = EIO;
+			break;
+		}
+		/* cps_delayns(10000000U); */
+		result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
+	} while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
+
+	return result;
+}
+
+/**
+ * Internal Function:Trigger function to poll and Ack IRQs
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK on success (Interrupt status high).
+ * @return EIO on poll time out.
+ * @return EINVAL checking status was not successful.
+ */
+static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd)
+{
+	uint32_t result = 0U;
+
+	/* Wait for PhyIndependent module to finish up ctl init sequence */
+	result =
+	    lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT,
+				   LPDDR4_CUSTOM_TIMEOUT_DELAY);
+
+	/* Ack to clear the PhyIndependent interrupt bit */
+	if (result == (uint32_t) CDN_EOK) {
+		result =
+		    lpddr4_ackphyindepinterrupt(pd,
+						LPDDR4_PHY_INDEP_INIT_DONE_BIT);
+	}
+	/* Wait for the CTL end of initialization */
+	if (result == (uint32_t) CDN_EOK) {
+		result =
+		    lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE,
+				      LPDDR4_CUSTOM_TIMEOUT_DELAY);
+	}
+	/* Ack to clear the Ctl interrupt bit */
+	if (result == (uint32_t) CDN_EOK) {
+		result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE);
+	}
+	return result;
+}
+
+/**
+ * Internal Function: Controller start sequence.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK on success.
+ * @return EINVAL starting controller was not successful.
+ */
+static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+	lpddr4_infotype infotype;
+
+	/* Set the PI_start to initiate leveling procedure */
+	regval =
+	    CPS_FLD_SET(LPDDR4__PI_START__FLD,
+			CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
+	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
+
+	/* Set the Ctl_start  */
+	regval =
+	    CPS_FLD_SET(LPDDR4__START__FLD,
+			CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
+
+	if (pd->infohandler != NULL) {
+		/* If a handler is registered, call it with the relevant information type */
+		infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
+		pd->infohandler(pd, infotype);
+	}
+
+	result = lpddr4_pollandackirq(pd);
+
+	return result;
+}
+
+/**
+ * Internal Function: To add the offset to given address.
+ * @param[in] addr Address to which the offset has to be added.
+ * @param[in] regOffset The offset
+ * @return regAddr The address value after the summation.
+ */
+static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr,
+					   uint32_t regoffset)
+{
+
+	volatile uint32_t *local_addr = addr;
+	/* Declaring as array to add the offset value. */
+	volatile uint32_t *regaddr = &local_addr[regoffset];
+	return regaddr;
+}
+
+/**
+ * Checks configuration object.
+ * @param[in] config Driver/hardware configuration required.
+ * @param[out] configSize Size of memory allocations required.
+ * @return CDN_EOK on success (requirements structure filled).
+ * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
+ */
+uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize)
+{
+	uint32_t result;
+
+	result = (uint32_t) (lpddr4_probesf(config, configsize));
+	if (result == (uint32_t) CDN_EOK) {
+		*configsize = (uint16_t) (sizeof(lpddr4_privatedata));
+	}
+	return result;
+}
+
+/**
+ * Init function to be called after LPDDR4_probe() to set up the driver configuration.
+ * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before
+ * calling  this API, init_settings should be initialized with base addresses for PHY Independent Module,
+ * Controller and PHY before calling this function.
+ * If callbacks are required for interrupt handling, these should also be configured in init_settings.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Specifies driver/hardware configuration.
+ * @return CDN_EOK on success
+ * @return EINVAL if illegal/inconsistent values in cfg.
+ * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s)
+ * required by 'config' parameters.
+ */
+uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
+{
+	uint32_t result = 0U;
+	uint16_t productid = 0U;
+	uint32_t version[2] = { 0, 0 };
+
+	result = lpddr4_initsf(pd, cfg);
+	if (result == (uint32_t) CDN_EOK) {
+		/* Validate Magic number */
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase;
+		productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD,
+						     CPS_REG_READ(&
+								  (ctlregbase->
+								   LPDDR4__CONTROLLER_ID__REG))));
+		version[0] =
+		    (uint32_t) (CPS_FLD_READ
+				(LPDDR4__CONTROLLER_VERSION_0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__CONTROLLER_VERSION_0__REG))));
+		version[1] =
+		    (uint32_t) (CPS_FLD_READ
+				(LPDDR4__CONTROLLER_VERSION_1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__CONTROLLER_VERSION_1__REG))));
+		if ((productid == PRODUCT_ID) && (version[0] == VERSION_0)
+		    && (version[1] == VERSION_1)) {
+			/* Populating configuration data to pD */
+			pd->ctlbase = ctlregbase;
+			pd->infohandler =
+			    (lpddr4_infocallback) cfg->infohandler;
+			pd->ctlinterrupthandler =
+			    (lpddr4_ctlcallback) cfg->ctlinterrupthandler;
+			pd->phyindepinterrupthandler =
+			    (lpddr4_phyindepcallback) cfg->
+			    phyindepinterrupthandler;
+		} else {
+			/* Magic number validation failed - Driver doesn't support given IP version */
+			result = (uint32_t) EOPNOTSUPP;
+		}
+	}
+	return result;
+}
+
+/**
+ * Start the driver.
+ * @param[in] pD Driver state info specific to this instance.
+ */
+uint32_t lpddr4_start(const lpddr4_privatedata * pd)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	result = lpddr4_startsf(pd);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Enable PI as the initiator for DRAM */
+		regval =
+		    CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD,
+				CPS_REG_READ(&
+					     (ctlregbase->
+					      LPDDR4__PI_INIT_LVL_EN__REG)));
+		regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
+		CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)),
+			      regval);
+
+		/* Start PI init sequence. */
+		result = lpddr4_startsequencecontroller(pd);
+	}
+	return result;
+}
+
+/**
+ * Read a register from the controller, PHY or PHY Independent Module
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
+ * @param[in] regOffset Register offset
+ * @param[out] regValue Register value read
+ * @return CDN_EOK on success.
+ * @return EINVAL if regOffset if out of range or regValue is NULL
+ */
+uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
+			uint32_t regoffset, uint32_t * regvalue)
+{
+	uint32_t result = 0U;
+
+	result = lpddr4_readregsf(pd, cpp, regvalue);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		if (cpp == LPDDR4_CTL_REGS) {
+			if (regoffset >= LPDDR4_CTL_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				*regvalue =
+				    CPS_REG_READ(lpddr4_addoffset
+						 (&(ctlregbase->DENALI_CTL_0),
+						  regoffset));
+			}
+		} else if (cpp == LPDDR4_PHY_REGS) {
+			if (regoffset >= LPDDR4_PHY_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				*regvalue =
+				    CPS_REG_READ(lpddr4_addoffset
+						 (&(ctlregbase->DENALI_PHY_0),
+						  regoffset));
+			}
+
+		} else {
+			if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				*regvalue =
+				    CPS_REG_READ(lpddr4_addoffset
+						 (&(ctlregbase->DENALI_PI_0),
+						  regoffset));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
+			 uint32_t regoffset, uint32_t regvalue)
+{
+	uint32_t result = 0U;
+
+	result = lpddr4_writeregsf(pd, cpp);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		if (cpp == LPDDR4_CTL_REGS) {
+			if (regoffset >= LPDDR4_CTL_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				CPS_REG_WRITE(lpddr4_addoffset
+					      (&(ctlregbase->DENALI_CTL_0),
+					       regoffset), regvalue);
+			}
+		} else if (cpp == LPDDR4_PHY_REGS) {
+			if (regoffset >= LPDDR4_PHY_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				CPS_REG_WRITE(lpddr4_addoffset
+					      (&(ctlregbase->DENALI_PHY_0),
+					       regoffset), regvalue);
+			}
+		} else {
+			if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
+				/* Return if user provider invalid register number */
+				result = EINVAL;
+			} else {
+				CPS_REG_WRITE(lpddr4_addoffset
+					      (&(ctlregbase->DENALI_PI_0),
+					       regoffset), regvalue);
+			}
+		}
+	}
+
+	return result;
+}
+
+static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,
+					 uint64_t * mmrvalue,
+					 uint8_t * mrrstatus)
+{
+
+	uint64_t lowerdata;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+	uint32_t result = (uint32_t) CDN_EOK;
+
+	/* Check if mode register read error interrupt occurred */
+	if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) {
+		/* Mode register read error interrupt, read MRR status register and return. */
+		*mrrstatus =
+		    (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD,
+					   CPS_REG_READ(&
+							(ctlregbase->
+							 LPDDR4__MRR_ERROR_STATUS__REG)));
+		*mmrvalue = 0;
+		result = EIO;
+	} else {
+		*mrrstatus = 0;
+		/* Mode register read was successful, read DATA */
+		lowerdata =
+		    CPS_REG_READ(&
+				 (ctlregbase->
+				  LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
+		*mmrvalue =
+		    CPS_REG_READ(&
+				 (ctlregbase->
+				  LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
+		*mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata);
+		/* Acknowledge MR_READ_DONE interrupt to clear it */
+		result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE);
+	}
+	return result;
+}
+
+uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd,
+			       uint32_t readmoderegval, uint64_t * mmrvalue,
+			       uint8_t * mmrstatus)
+{
+
+	uint32_t result = 0U;
+	uint32_t tdelay = 1000U;
+	uint32_t regval = 0U;
+
+	result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
+	if (result == (uint32_t) CDN_EOK) {
+
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Populate the calculated value to the register  */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__READ_MODEREG__REG)),
+				  readmoderegval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
+
+		/* Wait until the Read is done */
+		result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay);
+	}
+	if (result == (uint32_t) CDN_EOK) {
+		result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
+	}
+	return result;
+}
+
+static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd,
+					uint32_t writemoderegval)
+{
+
+	uint32_t result = (uint32_t) CDN_EOK;
+	uint32_t tdelay = 1000U;
+	uint32_t regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+	/* Populate the calculated value to the register  */
+	regval =
+	    CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD,
+			  CPS_REG_READ(&
+				       (ctlregbase->
+					LPDDR4__WRITE_MODEREG__REG)),
+			  writemoderegval);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
+
+	result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay);
+
+	return result;
+}
+
+uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd,
+			       uint32_t writemoderegval, uint8_t * mrwstatus)
+{
+	uint32_t result = 0U;
+
+	result = lpddr4_setmmrregistersf(pd, mrwstatus);
+	if (result == (uint32_t) CDN_EOK) {
+
+		/* Function call to trigger Mode register write */
+		result = lpddr4_writemmrregister(pd, writemoderegval);
+
+		if (result == (uint32_t) CDN_EOK) {
+			result =
+			    lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE);
+		}
+		/* Read the status of mode register write */
+		if (result == (uint32_t) CDN_EOK) {
+			lpddr4_ctlregs *ctlregbase =
+			    (lpddr4_ctlregs *) pd->ctlbase;
+			*mrwstatus =
+			    (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD,
+						   CPS_REG_READ(&
+								(ctlregbase->
+								 LPDDR4__MRW_STATUS__REG)));
+			if ((*mrwstatus) != 0U) {
+				result = EIO;
+			}
+		}
+	}
+
+	return result;
+}
+
+uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd,
+			       const lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+
+	result = lpddr4_writectlconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+
+		/* Iterate through CTL register numbers. */
+		for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
+			/* Check if the user has requested update */
+			if (regvalues->updatectlreg[regnum]) {
+				result =
+				    lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum,
+						    (uint32_t) (regvalues->
+								denalictlreg
+								[regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,
+				    const lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+
+	result = lpddr4_writephyindepconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+
+		/* Iterate through PHY Independent module register numbers. */
+		for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
+			/* Check if the user has requested update */
+			if (regvalues->updatephyindepreg[regnum]) {
+				result =
+				    lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS,
+						    regnum,
+						    (uint32_t) (regvalues->
+								denaliphyindepreg
+								[regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd,
+			       const lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+
+	result = lpddr4_writephyconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+
+		/* Iterate through PHY register numbers. */
+		for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
+			/* Check if the user has requested update */
+			if (regvalues->updatephyreg[regnum]) {
+				result =
+				    lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum,
+						    (uint32_t) (regvalues->
+								denaliphyreg
+								[regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd,
+			      lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+	result = lpddr4_readctlconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+		/* Iterate through CTL register numbers. */
+		for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
+			/* Check if the user has requested read (updateCtlReg=1) */
+			if (regvalues->updatectlreg[regnum]) {
+				result =
+				    lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum,
+						   (uint32_t *) (&regvalues->
+								 denalictlreg
+								 [regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,
+				   lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+
+	result = lpddr4_readphyindepconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+		/* Iterate through PHY Independent module register numbers. */
+		for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
+			/* Check if the user has requested read (updateCtlReg=1) */
+			if (regvalues->updatephyindepreg[regnum]) {
+				result =
+				    lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS,
+						   regnum,
+						   (uint32_t *) (&regvalues->
+								 denaliphyindepreg
+								 [regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd,
+			      lpddr4_reginitdata * regvalues)
+{
+	uint32_t result;
+	uint32_t regnum;
+
+	result = lpddr4_readphyconfigsf(pd, regvalues);
+	if (result == (uint32_t) CDN_EOK) {
+		/* Iterate through PHY register numbers. */
+		for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
+			/* Check if the user has requested read (updateCtlReg=1) */
+			if (regvalues->updatephyreg[regnum]) {
+				result =
+				    lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum,
+						   (uint32_t *) (&regvalues->
+								 denaliphyreg
+								 [regnum]));
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,
+				    uint64_t * mask)
+{
+	uint32_t result = 0U;
+	uint64_t lowermask = 0U;
+
+	result = lpddr4_getctlinterruptmasksf(pd, mask);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Reading the lower mask register */
+		lowermask =
+		    (uint64_t) (CPS_FLD_READ
+				(LPDDR4__INT_MASK_0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__INT_MASK_0__REG))));
+		/* Reading the upper mask register */
+		*mask =
+		    (uint64_t) (CPS_FLD_READ
+				(LPDDR4__INT_MASK_1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__INT_MASK_1__REG))));
+		/* Concatenate both register informations */
+		*mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask);
+	}
+	return result;
+}
+
+uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,
+				    const uint64_t * mask)
+{
+	uint32_t result;
+	uint32_t regval = 0;
+	const uint64_t ui64one = 1ULL;
+	const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U;
+
+	result = lpddr4_setctlinterruptmasksf(pd, mask);
+	if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) {
+		/* Return if the user given value is higher than the field width */
+		if (*mask >= (ui64one << ui32irqcount)) {
+			result = EINVAL;
+		}
+	}
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Extracting the lower 32 bits and writing to lower mask register */
+		regval = (uint32_t) (*mask & WORD_MASK);
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__INT_MASK_0__REG)),
+				  regval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
+
+		/* Extracting the upper 32 bits and writing to upper mask register */
+		regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK);
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__INT_MASK_1__REG)),
+				  regval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
+	}
+	return result;
+}
+
+uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
+				  lpddr4_ctlinterrupt intr, bool * irqstatus)
+{
+	uint32_t result;
+	uint32_t ctlirqstatus = 0;
+	uint32_t fieldshift = 0;
+
+	/* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
+	 * Value of 'interrupt' should be less than 64 */
+	result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		if ((uint32_t) intr >= WORD_SHIFT) {
+			ctlirqstatus =
+			    CPS_REG_READ(&
+					 (ctlregbase->
+					  LPDDR4__INT_STATUS_1__REG));
+			/* Reduce the shift value as we are considering upper register */
+			fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT);
+		} else {
+			ctlirqstatus =
+			    CPS_REG_READ(&
+					 (ctlregbase->
+					  LPDDR4__INT_STATUS_0__REG));
+			/* The shift value remains same for lower interrupt register */
+			fieldshift = (uint32_t) intr;
+		}
+
+		/* MISRA compliance (Shifting operation) check */
+		if (fieldshift < WORD_SHIFT) {
+			if (((ctlirqstatus >> fieldshift) & BIT_MASK) > 0U) {
+				*irqstatus = true;
+			} else {
+				*irqstatus = false;
+			}
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
+				lpddr4_ctlinterrupt intr)
+{
+	uint32_t result = 0;
+	uint32_t regval = 0;
+	uint32_t localinterrupt = (uint32_t) intr;
+
+	/* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
+	 * Value of 'interrupt' should be less than 64 */
+	result = lpddr4_ackctlinterruptsf(pd, intr);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Check if the requested bit is in upper register */
+		if (localinterrupt > WORD_SHIFT) {
+			localinterrupt =
+			    (localinterrupt - (uint32_t) WORD_SHIFT);
+			regval = ((uint32_t) BIT_MASK << localinterrupt);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
+				      regval);
+		} else {
+			regval = ((uint32_t) BIT_MASK << localinterrupt);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
+				      regval);
+		}
+	}
+
+	return result;
+}
+
+uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,
+					 uint32_t * mask)
+{
+	uint32_t result;
+
+	result = lpddr4_getphyindepinterruptmsf(pd, mask);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Reading mask register */
+		*mask =
+		    CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__PI_INT_MASK__REG)));
+	}
+	return result;
+}
+
+uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,
+					 const uint32_t * mask)
+{
+	uint32_t result;
+	uint32_t regval = 0;
+	const uint32_t ui32irqcount =
+	    (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
+
+	result = lpddr4_setphyindepinterruptmsf(pd, mask);
+	if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
+		/* Return if the user given value is higher than the field width */
+		if (*mask >= (1U << ui32irqcount)) {
+			result = EINVAL;
+		}
+	}
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Writing to the user requested interrupt mask */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__PI_INT_MASK__REG)),
+				  *mask);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
+	}
+	return result;
+}
+
+uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
+				       lpddr4_phyindepinterrupt intr,
+				       bool * irqstatus)
+{
+	uint32_t result = 0;
+	uint32_t phyindepirqstatus = 0;
+
+	result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus);
+	/* Confirming that the value of interrupt is less than register width */
+	if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Reading the requested bit to check interrupt status */
+		phyindepirqstatus =
+		    CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
+		*irqstatus =
+		    (((phyindepirqstatus >> (uint32_t) intr) & BIT_MASK) > 0U);
+	}
+	return result;
+}
+
+uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
+				     lpddr4_phyindepinterrupt intr)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+	uint32_t ui32shiftinterrupt = (uint32_t) intr;
+
+	result = lpddr4_ackphyindepinterruptsf(pd, intr);
+	/* Confirming that the value of interrupt is less than register width */
+	if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Write 1 to the requested bit to ACk the interrupt */
+		regval = ((uint32_t) BIT_MASK << ui32shiftinterrupt);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
+	}
+
+	return result;
+}
+
+/* Check for caTrainingError */
+static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,
+					lpddr4_debuginfo * debuginfo,
+					bool * errfoundptr)
+{
+
+	uint32_t regval;
+	uint32_t errbitmask = 0U;
+	uint32_t snum;
+	volatile uint32_t *regaddress;
+
+	regaddress =
+	    (volatile uint32_t
+	     *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
+	errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
+	/* PHY_ADR_CALVL_OBS1[4] – Right found
+	   PHY_ADR_CALVL_OBS1[5] – left found
+	   both the above fields should be high and below field should be zero.
+	   PHY_ADR_CALVL_OBS1[3:0] – calvl_state
+	 */
+	for (snum = 0U; snum < ASLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != CA_TRAIN_RL) {
+			debuginfo->catraingerror = true;
+			*errfoundptr = true;
+		}
+		regaddress =
+		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
+	}
+}
+
+/* Check for  wrLvlError */
+static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
+				   lpddr4_debuginfo * debuginfo,
+				   bool * errfoundptr)
+{
+
+	uint32_t regval;
+	uint32_t errbitmask = 0U;
+	uint32_t snum;
+	volatile uint32_t *regaddress;
+
+	regaddress =
+	    (volatile uint32_t
+	     *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
+	/* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
+	errbitmask = (BIT_MASK << 1) | (BIT_MASK);
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->wrlvlerror = true;
+			*errfoundptr = true;
+		}
+		regaddress =
+		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
+	}
+}
+
+/* Check for  GateLvlError */
+static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,
+				     lpddr4_debuginfo * debuginfo,
+				     bool * errfoundptr)
+{
+
+	uint32_t regval;
+	uint32_t errbitmask = 0U;
+	uint32_t snum;
+	volatile uint32_t *regaddress;
+
+	regaddress =
+	    (volatile uint32_t
+	     *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
+	/* PHY_GTLVL_STATUS_OBS[6] – gate_level min error
+	 * PHY_GTLVL_STATUS_OBS[7] – gate_level max error
+	 * All the above bit fields should be zero */
+	errbitmask = GATE_LVL_ERROR_FIELDS;
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->gatelvlerror = true;
+			*errfoundptr = true;
+		}
+		regaddress =
+		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
+	}
+}
+
+/* Check for  ReadLvlError */
+static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,
+				     lpddr4_debuginfo * debuginfo,
+				     bool * errfoundptr)
+{
+
+	uint32_t regval;
+	uint32_t errbitmask = 0U;
+	uint32_t snum;
+	volatile uint32_t *regaddress;
+
+	regaddress =
+	    (volatile uint32_t
+	     *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
+	/* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero.
+	   PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */
+	errbitmask = READ_LVL_ERROR_FIELDS;
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->readlvlerror = true;
+			*errfoundptr = true;
+		}
+		regaddress =
+		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
+	}
+}
+
+/* Check for  DqTrainingError */
+static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,
+					lpddr4_debuginfo * debuginfo,
+					bool * errfoundptr)
+{
+
+	uint32_t regval;
+	uint32_t errbitmask = 0U;
+	uint32_t snum;
+	volatile uint32_t *regaddress;
+
+	regaddress =
+	    (volatile uint32_t
+	     *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
+	/* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */
+	errbitmask = DQ_LVL_STATUS;
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->dqtrainingerror = true;
+			*errfoundptr = true;
+		}
+		regaddress =
+		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
+	}
+}
+
+/**
+ * Internal Function:For checking errors in training/levelling sequence.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] debugInfo pointer to debug information.
+ * @param[out] errFoundPtr pointer to return if error found.
+ * @return CDN_EOK on success (Interrupt status high).
+ * @return EINVAL checking or unmasking was not successful.
+ */
+static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd,
+				  lpddr4_debuginfo * debuginfo, bool errfound)
+{
+
+	bool localerrfound = errfound;
+
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+	if (localerrfound == false) {
+		/* Check for ca training error */
+		lpddr4_checkcatrainingerror(ctlregbase, debuginfo,
+					    &localerrfound);
+	}
+
+	if (localerrfound == false) {
+		/* Check for Write leveling error */
+		lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
+	}
+
+	if (localerrfound == false) {
+		/* Check for Gate leveling error */
+		lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
+	}
+
+	if (localerrfound == false) {
+		/* Check for Read leveling error */
+		lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
+	}
+
+	if (localerrfound == false) {
+		/* Check for DQ training error */
+		lpddr4_checkdqtrainingerror(ctlregbase, debuginfo,
+					    &localerrfound);
+	}
+	return localerrfound;
+}
+
+static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask,
+			    bool * errfoundptr, const uint32_t errorinfobits)
+{
+
+	uint32_t regval = 0U;
+
+	/* Read the respective observation register */
+	regval = CPS_REG_READ(reg);
+	/* Compare the error bit values */
+	if ((regval & errbitmask) != errorinfobits) {
+		*errfoundptr = true;
+	}
+	return *errfoundptr;
+}
+
+static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
+			     lpddr4_debuginfo * debuginfo, bool * errfoundptr)
+{
+
+	uint32_t errbitmask = (BIT_MASK << 0x1U) | (BIT_MASK);
+	/* Check PLL observation registers for PLL lock errors */
+
+	debuginfo->pllerror =
+	    lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
+			    errbitmask, errfoundptr, PLL_READY);
+	if (*errfoundptr == false) {
+		debuginfo->pllerror =
+		    lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
+				    errbitmask, errfoundptr, PLL_READY);
+	}
+
+	/* Check for IO Calibration errors */
+	if (*errfoundptr == false) {
+		debuginfo->iocaliberror =
+		    lpddr4_seterror(&
+				    (ctlregbase->
+				     LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
+				    IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+	}
+	if (*errfoundptr == false) {
+		debuginfo->iocaliberror =
+		    lpddr4_seterror(&
+				    (ctlregbase->
+				     LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
+				    IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+	}
+	if (*errfoundptr == false) {
+		debuginfo->iocaliberror =
+		    lpddr4_seterror(&
+				    (ctlregbase->
+				     LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
+				    IO_CALIB_FIELD, errfoundptr,
+				    IO_CALIB_STATE);
+	}
+}
+
+static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,
+				      const bool errorfound)
+{
+
+	uint32_t snum = 0U;
+	volatile uint32_t *regaddress;
+	uint32_t regval = 0U;
+
+	/* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */
+	if (errorfound == false) {
+		regaddress =
+		    (volatile uint32_t
+		     *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
+		/* Iterate through each PHY Data Slice */
+		for (snum = 0U; snum < DSLICE_NUM; snum++) {
+			regval =
+			    CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD,
+					CPS_REG_READ(regaddress));
+			CPS_REG_WRITE(regaddress, regval);
+			regaddress =
+			    lpddr4_addoffset(regaddress,
+					     (uint32_t) SLICE_WIDTH);
+		}
+	}
+}
+
+static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,
+					 const bool errorfound)
+{
+
+	uint32_t snum = 0U;
+	volatile uint32_t *regaddress;
+	uint32_t regval = 0U;
+
+	/* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */
+	if (errorfound == false) {
+		regaddress =
+		    (volatile uint32_t
+		     *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
+		/* Iterate through each PHY Address Slice */
+		for (snum = 0U; snum < ASLICE_NUM; snum++) {
+			regval =
+			    CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD,
+					CPS_REG_READ(regaddress));
+			CPS_REG_WRITE(regaddress, regval);
+			regaddress =
+			    lpddr4_addoffset(regaddress,
+					     (uint32_t) SLICE_WIDTH);
+		}
+	}
+}
+
+static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,
+			       const bool errorfound)
+{
+
+	/* Calling functions to enable snap shots of OBS registers */
+	lpddr4_setphysnapsettings(ctlregbase, errorfound);
+	lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
+}
+
+static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase,
+				    lpddr4_debuginfo * debuginfo,
+				    bool * errorfound)
+{
+
+	volatile uint32_t *regaddress;
+	uint32_t snum = 0U;
+	uint32_t errbitmask = 0U;
+	uint32_t regval = 0U;
+
+	/* Check for rxOffsetError */
+	if (*errorfound == false) {
+		regaddress =
+		    (volatile uint32_t
+		     *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
+		errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
+		/* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high
+		   phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */
+		for (snum = 0U; snum < DSLICE_NUM; snum++) {
+			regval =
+			    CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD,
+					 CPS_REG_READ(regaddress));
+			if ((regval & errbitmask) != RX_CAL_DONE) {
+				debuginfo->rxoffseterror = true;
+				*errorfound = true;
+			}
+			regaddress =
+			    lpddr4_addoffset(regaddress,
+					     (uint32_t) SLICE_WIDTH);
+		}
+	}
+}
+
+uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,
+				 lpddr4_debuginfo * debuginfo)
+{
+
+	uint32_t result = 0U;
+	bool errorfound = false;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getdebuginitinfosf(pd, debuginfo);
+	if (result == (uint32_t) CDN_EOK) {
+
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		lpddr4_seterrors(ctlregbase, debuginfo, &errorfound);
+		/* Function to setup Snap for OBS registers */
+		lpddr4_setsettings(ctlregbase, errorfound);
+		/* Function to check for Rx offset error */
+		lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
+		/* Function Check various levelling errors */
+		errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound);
+	}
+
+	if (errorfound == true) {
+		result = (uint32_t) EPROTO;
+	}
+
+	return result;
+}
+
+static void readpdwakeup(const lpddr4_ctlfspnum * fspnum,
+			 lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_PD_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_PD_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_PD_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,
+			      lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,
+			     lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
+				 lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
+				lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
+			       lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
+	}
+}
+
+static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
+				   lpddr4_ctlregs * ctlregbase,
+				   uint32_t * cycles)
+{
+
+	/* Read the appropriate register, based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		*cycles =
+		    CPS_FLD_READ
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		*cycles =
+		    CPS_FLD_READ
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		*cycles =
+		    CPS_FLD_READ
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+	}
+
+}
+
+static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,
+				     const lpddr4_lpiwakeupparam *
+				     lpiwakeupparam,
+				     const lpddr4_ctlfspnum * fspnum,
+				     uint32_t * cycles)
+{
+
+	/* Iterate through each of the Wake up parameter type */
+	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
+		/* Calling appropriate function for register read */
+		readpdwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
+		readsrshortwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
+		readsrlongwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
+		readsrlonggatewakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
+		readsrdpshortwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
+		readsrdplongwakeup(fspnum, ctlregbase, cycles);
+	} else {
+		/* Default function (sanity function already confirmed the variable value) */
+		readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
+	}
+}
+
+uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,
+				 const lpddr4_lpiwakeupparam * lpiwakeupparam,
+				 const lpddr4_ctlfspnum * fspnum,
+				 uint32_t * cycles)
+{
+
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
+					 cycles);
+	}
+	return result;
+}
+
+static void writepdwakeup(const lpddr4_ctlfspnum * fspnum,
+			  lpddr4_ctlregs * ctlregbase, const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_PD_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG),
+			      regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_PD_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG),
+			      regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_PD_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG),
+			      regval);
+	}
+}
+
+static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,
+			       lpddr4_ctlregs * ctlregbase,
+			       const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG),
+			      regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG),
+			      regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG),
+			      regval);
+	}
+}
+
+static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,
+			      lpddr4_ctlregs * ctlregbase,
+			      const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG),
+			      regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG),
+			      regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG),
+			      regval);
+	}
+}
+
+static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
+				  lpddr4_ctlregs * ctlregbase,
+				  const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG),
+			      regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG),
+			      regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG),
+			      regval);
+	}
+}
+
+static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
+				 lpddr4_ctlregs * ctlregbase,
+				 const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
+				lpddr4_ctlregs * ctlregbase,
+				const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)),
+				  *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
+				    lpddr4_ctlregs * ctlregbase,
+				    const uint32_t * cycles)
+{
+
+	uint32_t regval = 0U;
+	/* Write to appropriate register ,based on user given frequency. */
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval =
+		    CPS_FLD_WRITE
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
+		     *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG),
+			      regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval =
+		    CPS_FLD_WRITE
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
+		     *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG),
+			      regval);
+	} else {
+		/* Default register (sanity function already confirmed the variable value) */
+		regval =
+		    CPS_FLD_WRITE
+		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
+		     CPS_REG_READ(&
+				  (ctlregbase->
+				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
+		     *cycles);
+		CPS_REG_WRITE(&
+			      (ctlregbase->
+			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG),
+			      regval);
+	}
+}
+
+static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,
+				      const lpddr4_lpiwakeupparam *
+				      lpiwakeupparam,
+				      const lpddr4_ctlfspnum * fspnum,
+				      const uint32_t * cycles)
+{
+
+	/* Iterate through each of the Wake up parameter type */
+	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
+		/* Calling appropriate function for register write */
+		writepdwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
+		writesrshortwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
+		writesrlongwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
+		writesrlonggatewakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
+		writesrdpshortwakeup(fspnum, ctlregbase, cycles);
+	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
+		writesrdplongwakeup(fspnum, ctlregbase, cycles);
+	} else {
+		/* Default function (sanity function already confirmed the variable value) */
+		writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
+	}
+}
+
+uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,
+				 const lpddr4_lpiwakeupparam * lpiwakeupparam,
+				 const lpddr4_ctlfspnum * fspnum,
+				 const uint32_t * cycles)
+{
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+	if (result == (uint32_t) CDN_EOK) {
+		/* Return if the user given value is higher than the field width */
+		if (*cycles > NIBBLE_MASK) {
+			result = EINVAL;
+		}
+	}
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
+					  cycles);
+	}
+	return result;
+}
+
+uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd,
+			     lpddr4_eccenable * eccparam)
+{
+	uint32_t result = 0U;
+	uint32_t fldval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_geteccenablesf(pd, eccparam);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Reading the ECC_Enable field  from the register. */
+		fldval =
+		    CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD,
+				 CPS_REG_READ(&
+					      (ctlregbase->
+					       LPDDR4__ECC_ENABLE__REG)));
+		switch (fldval) {
+		case 3:
+			*eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
+			break;
+		case 2:
+			*eccparam = LPDDR4_ECC_ERR_DETECT;
+			break;
+		case 1:
+			*eccparam = LPDDR4_ECC_ENABLED;
+			break;
+		default:
+			/* Default ECC (Sanity function already confirmed the value to be in expected range.) */
+			*eccparam = LPDDR4_ECC_DISABLED;
+			break;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd,
+			     const lpddr4_eccenable * eccparam)
+{
+
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_seteccenablesf(pd, eccparam);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Updating the ECC_Enable field based on the user given value. */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__ECC_ENABLE__REG)),
+				  *eccparam);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
+	}
+	return result;
+}
+
+uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd,
+			     lpddr4_reducmode * mode)
+{
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getreducmodesf(pd, mode);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Read the value of reduc parameter. */
+		if (CPS_FLD_READ
+		    (LPDDR4__REDUC__FLD,
+		     CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) {
+			*mode = LPDDR4_REDUC_ON;
+		} else {
+			*mode = LPDDR4_REDUC_OFF;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd,
+			     const lpddr4_reducmode * mode)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_setreducmodesf(pd, mode);
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Setting to enable Half data path. */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__REDUC__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__REDUC__REG)), *mode);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
+	}
+	return result;
+}
+
+uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off)
+{
+
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getdbireadmodesf(pd, on_off);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Reading the field value from the register. */
+		if (CPS_FLD_READ
+		    (LPDDR4__RD_DBI_EN__FLD,
+		     CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) ==
+		    0U) {
+			*on_off = false;
+		} else {
+			*on_off = true;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off)
+{
+
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getdbireadmodesf(pd, on_off);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Reading the field value from the register. */
+		if (CPS_FLD_READ
+		    (LPDDR4__WR_DBI_EN__FLD,
+		     CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) ==
+		    0U) {
+			*on_off = false;
+		} else {
+			*on_off = true;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd,
+			   const lpddr4_dbimode * mode)
+{
+
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_setdbimodesf(pd, mode);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Updating the appropriate field value based on the user given mode */
+		if (*mode == LPDDR4_DBI_RD_ON) {
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__RD_DBI_EN__REG)),
+					  1U);
+		} else if (*mode == LPDDR4_DBI_RD_OFF) {
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__RD_DBI_EN__REG)),
+					  0U);
+		} else if (*mode == LPDDR4_DBI_WR_ON) {
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__WR_DBI_EN__REG)),
+					  1U);
+		} else {
+			/* Default field (Sanity function already confirmed the value to be in expected range.) */
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__WR_DBI_EN__REG)),
+					  0U);
+		}
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
+	}
+	return result;
+}
+
+uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd,
+			       const lpddr4_ctlfspnum * fspnum,
+			       uint32_t * cycles)
+{
+	uint32_t result = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_getrefreshratesf(pd, fspnum, cycles);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Selecting the appropriate register for the user requested Frequency */
+		switch (*fspnum) {
+		case LPDDR4_FSP_2:
+			*cycles =
+			    CPS_FLD_READ(LPDDR4__TREF_F2__FLD,
+					 CPS_REG_READ(&
+						      (ctlregbase->
+						       LPDDR4__TREF_F2__REG)));
+			break;
+		case LPDDR4_FSP_1:
+			*cycles =
+			    CPS_FLD_READ(LPDDR4__TREF_F1__FLD,
+					 CPS_REG_READ(&
+						      (ctlregbase->
+						       LPDDR4__TREF_F1__REG)));
+			break;
+		default:
+			/* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
+			*cycles =
+			    CPS_FLD_READ(LPDDR4__TREF_F0__FLD,
+					 CPS_REG_READ(&
+						      (ctlregbase->
+						       LPDDR4__TREF_F0__REG)));
+			break;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd,
+			       const lpddr4_ctlfspnum * fspnum,
+			       const uint32_t * cycles)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_setrefreshratesf(pd, fspnum, cycles);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+
+		/* Selecting the appropriate register for the user requested Frequency */
+		switch (*fspnum) {
+		case LPDDR4_FSP_2:
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__TREF_F2__REG)),
+					  *cycles);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG),
+				      regval);
+			break;
+		case LPDDR4_FSP_1:
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__TREF_F1__REG)),
+					  *cycles);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG),
+				      regval);
+			break;
+		default:
+			/* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
+			regval =
+			    CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD,
+					  CPS_REG_READ(&
+						       (ctlregbase->
+							LPDDR4__TREF_F0__REG)),
+					  *cycles);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG),
+				      regval);
+			break;
+		}
+	}
+	return result;
+}
+
+uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,
+				     const uint32_t trefinterval)
+{
+	uint32_t result = 0U;
+	uint32_t regval = 0U;
+
+	/* Calling Sanity Function to verify the input variables */
+	result = lpddr4_refreshperchipselectsf(pd);
+
+	if (result == (uint32_t) CDN_EOK) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
+		/* Setting tref_interval parameter to enable/disable Refresh per chip select. */
+		regval =
+		    CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD,
+				  CPS_REG_READ(&
+					       (ctlregbase->
+						LPDDR4__TREF_INTERVAL__REG)),
+				  trefinterval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG),
+			      regval);
+	}
+	return result;
+}
diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
new file mode 100644
index 0000000000..bc8059efd1
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
@@ -0,0 +1,825 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1024_READ_MASK				            0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK				           0x000107FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH   11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET          0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH              3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1025_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH             32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1026_READ_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK				           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH        16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK  0x00FF0000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH          8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH   4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1027_READ_MASK				            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK				           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH         11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT       24U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH        8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_1028_READ_MASK				            0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK				           0x01000707U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT       8U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH       3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET             0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET				  0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1029_READ_MASK				            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK				           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH				 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK   0x00007F00U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH           7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH            5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET              0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1030_READ_MASK				            0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK				           0x01070301U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET    0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK				 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT				         8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH				         2U
+#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK     0x00070000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH             3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH				      1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR				      0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET				      0U
+#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_1031_READ_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH				    27U
+#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
+#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1032_READ_MASK				            0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK				           0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH				     6U
+#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
+#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_1033_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH				32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_1034_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH       32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_1035_READ_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK          0x000007FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH				 11U
+#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
+
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH            11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
+
+#define LPDDR4__DENALI_PHY_1036_READ_MASK				            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH				   11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
+
+#define LPDDR4__DENALI_PHY_1037_READ_MASK				            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_1038_READ_MASK				            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK				           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK      0x03000000U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH              2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1039_READ_MASK				            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK				           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH           2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK  0x00000F00U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH          4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH  9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_1040_READ_MASK				            0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK				           0x07000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET             0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET          0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
+
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK     0x07000000U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH             3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1041_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
+#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
+
+#define LPDDR4__DENALI_PHY_1042_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH              32U
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
+#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
+
+#define LPDDR4__DENALI_PHY_1043_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH				  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
+
+#define LPDDR4__DENALI_PHY_1044_READ_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH				  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
+
+#define LPDDR4__DENALI_PHY_1045_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
+
+#define LPDDR4__DENALI_PHY_1046_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
+
+#define LPDDR4__DENALI_PHY_1047_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
+
+#define LPDDR4__DENALI_PHY_1048_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
+
+#define LPDDR4__DENALI_PHY_1049_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
+
+#define LPDDR4__DENALI_PHY_1050_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
+
+#define LPDDR4__DENALI_PHY_1051_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
+
+#define LPDDR4__DENALI_PHY_1052_READ_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH				  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
+
+#define LPDDR4__DENALI_PHY_1053_READ_MASK				            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH				    24U
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
+
+#define LPDDR4__DENALI_PHY_1054_READ_MASK				            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK				           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH          10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK             0x003F0000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH				     6U
+#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK             0x3F000000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH				     6U
+#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055_READ_MASK				            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK				           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH             6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH             6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH           4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT				24U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH				 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1056_READ_MASK				            0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK				           0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK      0x00000003U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH              2U
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK   0xFF000000U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057_READ_MASK				            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK				           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH  1U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR  0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET  0U
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_1058_READ_MASK				            0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK				           0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH               8U
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK            0x00030000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH				    2U
+#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK      0x3F000000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH              6U
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
+
+#define LPDDR4__DENALI_PHY_1059_READ_MASK				            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK				           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH         8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET             0U
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_1060_READ_MASK				            0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK				           0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET				 0U
+#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK        0x00003F00U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH				6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK   0x07FF0000U
+#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH          11U
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
+
+#define LPDDR4__DENALI_PHY_1061_READ_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK				           0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH				9U
+#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
+
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK   0x01FF0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH           9U
+#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
+#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
+
+#define LPDDR4__DENALI_PHY_1062_READ_MASK				            0x01010000U
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK				           0x01010000U
+#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH       9U
+#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062
+#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0
+
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET        0U
+#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0
+
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH   1U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR   0U
+#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET   0U
+#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062
+#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0
+
+#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U
+#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
+#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
+
+#define LPDDR4__DENALI_PHY_1064_READ_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH				  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK       0x00000700U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH               3U
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK           0x07FF0000U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH				  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1065_READ_MASK				            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK				           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1066_READ_MASK				            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1067_READ_MASK				            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1068_READ_MASK				            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1069_READ_MASK				            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1070_READ_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070_WRITE_MASK				           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_1071_READ_MASK				            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071_WRITE_MASK				           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1072_READ_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072_WRITE_MASK				           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_1073_READ_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_1073_WRITE_MASK				           0x0000000FU
+#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_1074_READ_MASK				            0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074_WRITE_MASK				           0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
+#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1075_READ_MASK				            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075_WRITE_MASK				           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET              0U
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075
+#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH            8U
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075
+#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
new file mode 100644
index 0000000000..213e569488
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
@@ -0,0 +1,1546 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_data_slice_2_macros.h"
+#include "lpddr4_data_slice_3_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+	volatile uint32_t DENALI_CTL_0;
+	volatile uint32_t DENALI_CTL_1;
+	volatile uint32_t DENALI_CTL_2;
+	volatile uint32_t DENALI_CTL_3;
+	volatile uint32_t DENALI_CTL_4;
+	volatile uint32_t DENALI_CTL_5;
+	volatile uint32_t DENALI_CTL_6;
+	volatile uint32_t DENALI_CTL_7;
+	volatile uint32_t DENALI_CTL_8;
+	volatile uint32_t DENALI_CTL_9;
+	volatile uint32_t DENALI_CTL_10;
+	volatile uint32_t DENALI_CTL_11;
+	volatile uint32_t DENALI_CTL_12;
+	volatile uint32_t DENALI_CTL_13;
+	volatile uint32_t DENALI_CTL_14;
+	volatile uint32_t DENALI_CTL_15;
+	volatile uint32_t DENALI_CTL_16;
+	volatile uint32_t DENALI_CTL_17;
+	volatile uint32_t DENALI_CTL_18;
+	volatile uint32_t DENALI_CTL_19;
+	volatile uint32_t DENALI_CTL_20;
+	volatile uint32_t DENALI_CTL_21;
+	volatile uint32_t DENALI_CTL_22;
+	volatile uint32_t DENALI_CTL_23;
+	volatile uint32_t DENALI_CTL_24;
+	volatile uint32_t DENALI_CTL_25;
+	volatile uint32_t DENALI_CTL_26;
+	volatile uint32_t DENALI_CTL_27;
+	volatile uint32_t DENALI_CTL_28;
+	volatile uint32_t DENALI_CTL_29;
+	volatile uint32_t DENALI_CTL_30;
+	volatile uint32_t DENALI_CTL_31;
+	volatile uint32_t DENALI_CTL_32;
+	volatile uint32_t DENALI_CTL_33;
+	volatile uint32_t DENALI_CTL_34;
+	volatile uint32_t DENALI_CTL_35;
+	volatile uint32_t DENALI_CTL_36;
+	volatile uint32_t DENALI_CTL_37;
+	volatile uint32_t DENALI_CTL_38;
+	volatile uint32_t DENALI_CTL_39;
+	volatile uint32_t DENALI_CTL_40;
+	volatile uint32_t DENALI_CTL_41;
+	volatile uint32_t DENALI_CTL_42;
+	volatile uint32_t DENALI_CTL_43;
+	volatile uint32_t DENALI_CTL_44;
+	volatile uint32_t DENALI_CTL_45;
+	volatile uint32_t DENALI_CTL_46;
+	volatile uint32_t DENALI_CTL_47;
+	volatile uint32_t DENALI_CTL_48;
+	volatile uint32_t DENALI_CTL_49;
+	volatile uint32_t DENALI_CTL_50;
+	volatile uint32_t DENALI_CTL_51;
+	volatile uint32_t DENALI_CTL_52;
+	volatile uint32_t DENALI_CTL_53;
+	volatile uint32_t DENALI_CTL_54;
+	volatile uint32_t DENALI_CTL_55;
+	volatile uint32_t DENALI_CTL_56;
+	volatile uint32_t DENALI_CTL_57;
+	volatile uint32_t DENALI_CTL_58;
+	volatile uint32_t DENALI_CTL_59;
+	volatile uint32_t DENALI_CTL_60;
+	volatile uint32_t DENALI_CTL_61;
+	volatile uint32_t DENALI_CTL_62;
+	volatile uint32_t DENALI_CTL_63;
+	volatile uint32_t DENALI_CTL_64;
+	volatile uint32_t DENALI_CTL_65;
+	volatile uint32_t DENALI_CTL_66;
+	volatile uint32_t DENALI_CTL_67;
+	volatile uint32_t DENALI_CTL_68;
+	volatile uint32_t DENALI_CTL_69;
+	volatile uint32_t DENALI_CTL_70;
+	volatile uint32_t DENALI_CTL_71;
+	volatile uint32_t DENALI_CTL_72;
+	volatile uint32_t DENALI_CTL_73;
+	volatile uint32_t DENALI_CTL_74;
+	volatile uint32_t DENALI_CTL_75;
+	volatile uint32_t DENALI_CTL_76;
+	volatile uint32_t DENALI_CTL_77;
+	volatile uint32_t DENALI_CTL_78;
+	volatile uint32_t DENALI_CTL_79;
+	volatile uint32_t DENALI_CTL_80;
+	volatile uint32_t DENALI_CTL_81;
+	volatile uint32_t DENALI_CTL_82;
+	volatile uint32_t DENALI_CTL_83;
+	volatile uint32_t DENALI_CTL_84;
+	volatile uint32_t DENALI_CTL_85;
+	volatile uint32_t DENALI_CTL_86;
+	volatile uint32_t DENALI_CTL_87;
+	volatile uint32_t DENALI_CTL_88;
+	volatile uint32_t DENALI_CTL_89;
+	volatile uint32_t DENALI_CTL_90;
+	volatile uint32_t DENALI_CTL_91;
+	volatile uint32_t DENALI_CTL_92;
+	volatile uint32_t DENALI_CTL_93;
+	volatile uint32_t DENALI_CTL_94;
+	volatile uint32_t DENALI_CTL_95;
+	volatile uint32_t DENALI_CTL_96;
+	volatile uint32_t DENALI_CTL_97;
+	volatile uint32_t DENALI_CTL_98;
+	volatile uint32_t DENALI_CTL_99;
+	volatile uint32_t DENALI_CTL_100;
+	volatile uint32_t DENALI_CTL_101;
+	volatile uint32_t DENALI_CTL_102;
+	volatile uint32_t DENALI_CTL_103;
+	volatile uint32_t DENALI_CTL_104;
+	volatile uint32_t DENALI_CTL_105;
+	volatile uint32_t DENALI_CTL_106;
+	volatile uint32_t DENALI_CTL_107;
+	volatile uint32_t DENALI_CTL_108;
+	volatile uint32_t DENALI_CTL_109;
+	volatile uint32_t DENALI_CTL_110;
+	volatile uint32_t DENALI_CTL_111;
+	volatile uint32_t DENALI_CTL_112;
+	volatile uint32_t DENALI_CTL_113;
+	volatile uint32_t DENALI_CTL_114;
+	volatile uint32_t DENALI_CTL_115;
+	volatile uint32_t DENALI_CTL_116;
+	volatile uint32_t DENALI_CTL_117;
+	volatile uint32_t DENALI_CTL_118;
+	volatile uint32_t DENALI_CTL_119;
+	volatile uint32_t DENALI_CTL_120;
+	volatile uint32_t DENALI_CTL_121;
+	volatile uint32_t DENALI_CTL_122;
+	volatile uint32_t DENALI_CTL_123;
+	volatile uint32_t DENALI_CTL_124;
+	volatile uint32_t DENALI_CTL_125;
+	volatile uint32_t DENALI_CTL_126;
+	volatile uint32_t DENALI_CTL_127;
+	volatile uint32_t DENALI_CTL_128;
+	volatile uint32_t DENALI_CTL_129;
+	volatile uint32_t DENALI_CTL_130;
+	volatile uint32_t DENALI_CTL_131;
+	volatile uint32_t DENALI_CTL_132;
+	volatile uint32_t DENALI_CTL_133;
+	volatile uint32_t DENALI_CTL_134;
+	volatile uint32_t DENALI_CTL_135;
+	volatile uint32_t DENALI_CTL_136;
+	volatile uint32_t DENALI_CTL_137;
+	volatile uint32_t DENALI_CTL_138;
+	volatile uint32_t DENALI_CTL_139;
+	volatile uint32_t DENALI_CTL_140;
+	volatile uint32_t DENALI_CTL_141;
+	volatile uint32_t DENALI_CTL_142;
+	volatile uint32_t DENALI_CTL_143;
+	volatile uint32_t DENALI_CTL_144;
+	volatile uint32_t DENALI_CTL_145;
+	volatile uint32_t DENALI_CTL_146;
+	volatile uint32_t DENALI_CTL_147;
+	volatile uint32_t DENALI_CTL_148;
+	volatile uint32_t DENALI_CTL_149;
+	volatile uint32_t DENALI_CTL_150;
+	volatile uint32_t DENALI_CTL_151;
+	volatile uint32_t DENALI_CTL_152;
+	volatile uint32_t DENALI_CTL_153;
+	volatile uint32_t DENALI_CTL_154;
+	volatile uint32_t DENALI_CTL_155;
+	volatile uint32_t DENALI_CTL_156;
+	volatile uint32_t DENALI_CTL_157;
+	volatile uint32_t DENALI_CTL_158;
+	volatile uint32_t DENALI_CTL_159;
+	volatile uint32_t DENALI_CTL_160;
+	volatile uint32_t DENALI_CTL_161;
+	volatile uint32_t DENALI_CTL_162;
+	volatile uint32_t DENALI_CTL_163;
+	volatile uint32_t DENALI_CTL_164;
+	volatile uint32_t DENALI_CTL_165;
+	volatile uint32_t DENALI_CTL_166;
+	volatile uint32_t DENALI_CTL_167;
+	volatile uint32_t DENALI_CTL_168;
+	volatile uint32_t DENALI_CTL_169;
+	volatile uint32_t DENALI_CTL_170;
+	volatile uint32_t DENALI_CTL_171;
+	volatile uint32_t DENALI_CTL_172;
+	volatile uint32_t DENALI_CTL_173;
+	volatile uint32_t DENALI_CTL_174;
+	volatile uint32_t DENALI_CTL_175;
+	volatile uint32_t DENALI_CTL_176;
+	volatile uint32_t DENALI_CTL_177;
+	volatile uint32_t DENALI_CTL_178;
+	volatile uint32_t DENALI_CTL_179;
+	volatile uint32_t DENALI_CTL_180;
+	volatile uint32_t DENALI_CTL_181;
+	volatile uint32_t DENALI_CTL_182;
+	volatile uint32_t DENALI_CTL_183;
+	volatile uint32_t DENALI_CTL_184;
+	volatile uint32_t DENALI_CTL_185;
+	volatile uint32_t DENALI_CTL_186;
+	volatile uint32_t DENALI_CTL_187;
+	volatile uint32_t DENALI_CTL_188;
+	volatile uint32_t DENALI_CTL_189;
+	volatile uint32_t DENALI_CTL_190;
+	volatile uint32_t DENALI_CTL_191;
+	volatile uint32_t DENALI_CTL_192;
+	volatile uint32_t DENALI_CTL_193;
+	volatile uint32_t DENALI_CTL_194;
+	volatile uint32_t DENALI_CTL_195;
+	volatile uint32_t DENALI_CTL_196;
+	volatile uint32_t DENALI_CTL_197;
+	volatile uint32_t DENALI_CTL_198;
+	volatile uint32_t DENALI_CTL_199;
+	volatile uint32_t DENALI_CTL_200;
+	volatile uint32_t DENALI_CTL_201;
+	volatile uint32_t DENALI_CTL_202;
+	volatile uint32_t DENALI_CTL_203;
+	volatile uint32_t DENALI_CTL_204;
+	volatile uint32_t DENALI_CTL_205;
+	volatile uint32_t DENALI_CTL_206;
+	volatile uint32_t DENALI_CTL_207;
+	volatile uint32_t DENALI_CTL_208;
+	volatile uint32_t DENALI_CTL_209;
+	volatile uint32_t DENALI_CTL_210;
+	volatile uint32_t DENALI_CTL_211;
+	volatile uint32_t DENALI_CTL_212;
+	volatile uint32_t DENALI_CTL_213;
+	volatile uint32_t DENALI_CTL_214;
+	volatile uint32_t DENALI_CTL_215;
+	volatile uint32_t DENALI_CTL_216;
+	volatile uint32_t DENALI_CTL_217;
+	volatile uint32_t DENALI_CTL_218;
+	volatile uint32_t DENALI_CTL_219;
+	volatile uint32_t DENALI_CTL_220;
+	volatile uint32_t DENALI_CTL_221;
+	volatile uint32_t DENALI_CTL_222;
+	volatile uint32_t DENALI_CTL_223;
+	volatile uint32_t DENALI_CTL_224;
+	volatile uint32_t DENALI_CTL_225;
+	volatile uint32_t DENALI_CTL_226;
+	volatile uint32_t DENALI_CTL_227;
+	volatile uint32_t DENALI_CTL_228;
+	volatile uint32_t DENALI_CTL_229;
+	volatile uint32_t DENALI_CTL_230;
+	volatile uint32_t DENALI_CTL_231;
+	volatile uint32_t DENALI_CTL_232;
+	volatile uint32_t DENALI_CTL_233;
+	volatile uint32_t DENALI_CTL_234;
+	volatile uint32_t DENALI_CTL_235;
+	volatile uint32_t DENALI_CTL_236;
+	volatile uint32_t DENALI_CTL_237;
+	volatile uint32_t DENALI_CTL_238;
+	volatile uint32_t DENALI_CTL_239;
+	volatile uint32_t DENALI_CTL_240;
+	volatile uint32_t DENALI_CTL_241;
+	volatile uint32_t DENALI_CTL_242;
+	volatile uint32_t DENALI_CTL_243;
+	volatile uint32_t DENALI_CTL_244;
+	volatile uint32_t DENALI_CTL_245;
+	volatile uint32_t DENALI_CTL_246;
+	volatile uint32_t DENALI_CTL_247;
+	volatile uint32_t DENALI_CTL_248;
+	volatile uint32_t DENALI_CTL_249;
+	volatile uint32_t DENALI_CTL_250;
+	volatile uint32_t DENALI_CTL_251;
+	volatile uint32_t DENALI_CTL_252;
+	volatile uint32_t DENALI_CTL_253;
+	volatile uint32_t DENALI_CTL_254;
+	volatile uint32_t DENALI_CTL_255;
+	volatile uint32_t DENALI_CTL_256;
+	volatile uint32_t DENALI_CTL_257;
+	volatile uint32_t DENALI_CTL_258;
+	volatile uint32_t DENALI_CTL_259;
+	volatile uint32_t DENALI_CTL_260;
+	volatile uint32_t DENALI_CTL_261;
+	volatile uint32_t DENALI_CTL_262;
+	volatile uint32_t DENALI_CTL_263;
+	volatile uint32_t DENALI_CTL_264;
+	volatile uint32_t DENALI_CTL_265;
+	volatile uint32_t DENALI_CTL_266;
+	volatile uint32_t DENALI_CTL_267;
+	volatile uint32_t DENALI_CTL_268;
+	volatile uint32_t DENALI_CTL_269;
+	volatile uint32_t DENALI_CTL_270;
+	volatile uint32_t DENALI_CTL_271;
+	volatile uint32_t DENALI_CTL_272;
+	volatile uint32_t DENALI_CTL_273;
+	volatile uint32_t DENALI_CTL_274;
+	volatile uint32_t DENALI_CTL_275;
+	volatile uint32_t DENALI_CTL_276;
+	volatile uint32_t DENALI_CTL_277;
+	volatile uint32_t DENALI_CTL_278;
+	volatile uint32_t DENALI_CTL_279;
+	volatile uint32_t DENALI_CTL_280;
+	volatile uint32_t DENALI_CTL_281;
+	volatile uint32_t DENALI_CTL_282;
+	volatile uint32_t DENALI_CTL_283;
+	volatile uint32_t DENALI_CTL_284;
+	volatile uint32_t DENALI_CTL_285;
+	volatile uint32_t DENALI_CTL_286;
+	volatile uint32_t DENALI_CTL_287;
+	volatile uint32_t DENALI_CTL_288;
+	volatile uint32_t DENALI_CTL_289;
+	volatile uint32_t DENALI_CTL_290;
+	volatile uint32_t DENALI_CTL_291;
+	volatile uint32_t DENALI_CTL_292;
+	volatile uint32_t DENALI_CTL_293;
+	volatile uint32_t DENALI_CTL_294;
+	volatile uint32_t DENALI_CTL_295;
+	volatile uint32_t DENALI_CTL_296;
+	volatile uint32_t DENALI_CTL_297;
+	volatile uint32_t DENALI_CTL_298;
+	volatile uint32_t DENALI_CTL_299;
+	volatile uint32_t DENALI_CTL_300;
+	volatile uint32_t DENALI_CTL_301;
+	volatile uint32_t DENALI_CTL_302;
+	volatile uint32_t DENALI_CTL_303;
+	volatile uint32_t DENALI_CTL_304;
+	volatile uint32_t DENALI_CTL_305;
+	volatile uint32_t DENALI_CTL_306;
+	volatile uint32_t DENALI_CTL_307;
+	volatile uint32_t DENALI_CTL_308;
+	volatile uint32_t DENALI_CTL_309;
+	volatile uint32_t DENALI_CTL_310;
+	volatile uint32_t DENALI_CTL_311;
+	volatile uint32_t DENALI_CTL_312;
+	volatile uint32_t DENALI_CTL_313;
+	volatile uint32_t DENALI_CTL_314;
+	volatile uint32_t DENALI_CTL_315;
+	volatile uint32_t DENALI_CTL_316;
+	volatile uint32_t DENALI_CTL_317;
+	volatile uint32_t DENALI_CTL_318;
+	volatile uint32_t DENALI_CTL_319;
+	volatile uint32_t DENALI_CTL_320;
+	volatile uint32_t DENALI_CTL_321;
+	volatile uint32_t DENALI_CTL_322;
+	volatile uint32_t DENALI_CTL_323;
+	volatile uint32_t DENALI_CTL_324;
+	volatile uint32_t DENALI_CTL_325;
+	volatile uint32_t DENALI_CTL_326;
+	volatile uint32_t DENALI_CTL_327;
+	volatile uint32_t DENALI_CTL_328;
+	volatile uint32_t DENALI_CTL_329;
+	volatile uint32_t DENALI_CTL_330;
+	volatile uint32_t DENALI_CTL_331;
+	volatile uint32_t DENALI_CTL_332;
+	volatile uint32_t DENALI_CTL_333;
+	volatile uint32_t DENALI_CTL_334;
+	volatile uint32_t DENALI_CTL_335;
+	volatile uint32_t DENALI_CTL_336;
+	volatile uint32_t DENALI_CTL_337;
+	volatile uint32_t DENALI_CTL_338;
+	volatile uint32_t DENALI_CTL_339;
+	volatile uint32_t DENALI_CTL_340;
+	volatile uint32_t DENALI_CTL_341;
+	volatile uint32_t DENALI_CTL_342;
+	volatile uint32_t DENALI_CTL_343;
+	volatile uint32_t DENALI_CTL_344;
+	volatile uint32_t DENALI_CTL_345;
+	volatile uint32_t DENALI_CTL_346;
+	volatile uint32_t DENALI_CTL_347;
+	volatile uint32_t DENALI_CTL_348;
+	volatile uint32_t DENALI_CTL_349;
+	volatile uint32_t DENALI_CTL_350;
+	volatile uint32_t DENALI_CTL_351;
+	volatile uint32_t DENALI_CTL_352;
+	volatile uint32_t DENALI_CTL_353;
+	volatile uint32_t DENALI_CTL_354;
+	volatile uint32_t DENALI_CTL_355;
+	volatile uint32_t DENALI_CTL_356;
+	volatile uint32_t DENALI_CTL_357;
+	volatile uint32_t DENALI_CTL_358;
+	volatile uint32_t DENALI_CTL_359;
+	volatile uint32_t DENALI_CTL_360;
+	volatile uint32_t DENALI_CTL_361;
+	volatile uint32_t DENALI_CTL_362;
+	volatile uint32_t DENALI_CTL_363;
+	volatile uint32_t DENALI_CTL_364;
+	volatile uint32_t DENALI_CTL_365;
+	volatile uint32_t DENALI_CTL_366;
+	volatile uint32_t DENALI_CTL_367;
+	volatile uint32_t DENALI_CTL_368;
+	volatile uint32_t DENALI_CTL_369;
+	volatile uint32_t DENALI_CTL_370;
+	volatile uint32_t DENALI_CTL_371;
+	volatile uint32_t DENALI_CTL_372;
+	volatile uint32_t DENALI_CTL_373;
+	volatile uint32_t DENALI_CTL_374;
+	volatile uint32_t DENALI_CTL_375;
+	volatile uint32_t DENALI_CTL_376;
+	volatile uint32_t DENALI_CTL_377;
+	volatile uint32_t DENALI_CTL_378;
+	volatile uint32_t DENALI_CTL_379;
+	volatile uint32_t DENALI_CTL_380;
+	volatile uint32_t DENALI_CTL_381;
+	volatile uint32_t DENALI_CTL_382;
+	volatile uint32_t DENALI_CTL_383;
+	volatile uint32_t DENALI_CTL_384;
+	volatile uint32_t DENALI_CTL_385;
+	volatile uint32_t DENALI_CTL_386;
+	volatile uint32_t DENALI_CTL_387;
+	volatile uint32_t DENALI_CTL_388;
+	volatile uint32_t DENALI_CTL_389;
+	volatile uint32_t DENALI_CTL_390;
+	volatile uint32_t DENALI_CTL_391;
+	volatile uint32_t DENALI_CTL_392;
+	volatile uint32_t DENALI_CTL_393;
+	volatile uint32_t DENALI_CTL_394;
+	volatile uint32_t DENALI_CTL_395;
+	volatile uint32_t DENALI_CTL_396;
+	volatile uint32_t DENALI_CTL_397;
+	volatile uint32_t DENALI_CTL_398;
+	volatile uint32_t DENALI_CTL_399;
+	volatile uint32_t DENALI_CTL_400;
+	volatile uint32_t DENALI_CTL_401;
+	volatile uint32_t DENALI_CTL_402;
+	volatile uint32_t DENALI_CTL_403;
+	volatile uint32_t DENALI_CTL_404;
+	volatile uint32_t DENALI_CTL_405;
+	volatile uint32_t DENALI_CTL_406;
+	volatile uint32_t DENALI_CTL_407;
+	volatile uint32_t DENALI_CTL_408;
+	volatile uint32_t DENALI_CTL_409;
+	volatile uint32_t DENALI_CTL_410;
+	volatile uint32_t DENALI_CTL_411;
+	volatile uint32_t DENALI_CTL_412;
+	volatile uint32_t DENALI_CTL_413;
+	volatile uint32_t DENALI_CTL_414;
+	volatile uint32_t DENALI_CTL_415;
+	volatile uint32_t DENALI_CTL_416;
+	volatile uint32_t DENALI_CTL_417;
+	volatile uint32_t DENALI_CTL_418;
+	volatile uint32_t DENALI_CTL_419;
+	volatile uint32_t DENALI_CTL_420;
+	volatile uint32_t DENALI_CTL_421;
+	volatile uint32_t DENALI_CTL_422;
+	volatile uint32_t DENALI_CTL_423;
+	volatile uint32_t DENALI_CTL_424;
+	volatile uint32_t DENALI_CTL_425;
+	volatile uint32_t DENALI_CTL_426;
+	volatile uint32_t DENALI_CTL_427;
+	volatile uint32_t DENALI_CTL_428;
+	volatile uint32_t DENALI_CTL_429;
+	volatile uint32_t DENALI_CTL_430;
+	volatile uint32_t DENALI_CTL_431;
+	volatile uint32_t DENALI_CTL_432;
+	volatile uint32_t DENALI_CTL_433;
+	volatile uint32_t DENALI_CTL_434;
+	volatile uint32_t DENALI_CTL_435;
+	volatile uint32_t DENALI_CTL_436;
+	volatile uint32_t DENALI_CTL_437;
+	volatile uint32_t DENALI_CTL_438;
+	volatile uint32_t DENALI_CTL_439;
+	volatile uint32_t DENALI_CTL_440;
+	volatile uint32_t DENALI_CTL_441;
+	volatile uint32_t DENALI_CTL_442;
+	volatile uint32_t DENALI_CTL_443;
+	volatile uint32_t DENALI_CTL_444;
+	volatile uint32_t DENALI_CTL_445;
+	volatile uint32_t DENALI_CTL_446;
+	volatile uint32_t DENALI_CTL_447;
+	volatile uint32_t DENALI_CTL_448;
+	volatile uint32_t DENALI_CTL_449;
+	volatile uint32_t DENALI_CTL_450;
+	volatile uint32_t DENALI_CTL_451;
+	volatile uint32_t DENALI_CTL_452;
+	volatile uint32_t DENALI_CTL_453;
+	volatile uint32_t DENALI_CTL_454;
+	volatile uint32_t DENALI_CTL_455;
+	volatile uint32_t DENALI_CTL_456;
+	volatile uint32_t DENALI_CTL_457;
+	volatile uint32_t DENALI_CTL_458;
+	volatile char pad__0[0x18D4U];
+	volatile uint32_t DENALI_PI_0;
+	volatile uint32_t DENALI_PI_1;
+	volatile uint32_t DENALI_PI_2;
+	volatile uint32_t DENALI_PI_3;
+	volatile uint32_t DENALI_PI_4;
+	volatile uint32_t DENALI_PI_5;
+	volatile uint32_t DENALI_PI_6;
+	volatile uint32_t DENALI_PI_7;
+	volatile uint32_t DENALI_PI_8;
+	volatile uint32_t DENALI_PI_9;
+	volatile uint32_t DENALI_PI_10;
+	volatile uint32_t DENALI_PI_11;
+	volatile uint32_t DENALI_PI_12;
+	volatile uint32_t DENALI_PI_13;
+	volatile uint32_t DENALI_PI_14;
+	volatile uint32_t DENALI_PI_15;
+	volatile uint32_t DENALI_PI_16;
+	volatile uint32_t DENALI_PI_17;
+	volatile uint32_t DENALI_PI_18;
+	volatile uint32_t DENALI_PI_19;
+	volatile uint32_t DENALI_PI_20;
+	volatile uint32_t DENALI_PI_21;
+	volatile uint32_t DENALI_PI_22;
+	volatile uint32_t DENALI_PI_23;
+	volatile uint32_t DENALI_PI_24;
+	volatile uint32_t DENALI_PI_25;
+	volatile uint32_t DENALI_PI_26;
+	volatile uint32_t DENALI_PI_27;
+	volatile uint32_t DENALI_PI_28;
+	volatile uint32_t DENALI_PI_29;
+	volatile uint32_t DENALI_PI_30;
+	volatile uint32_t DENALI_PI_31;
+	volatile uint32_t DENALI_PI_32;
+	volatile uint32_t DENALI_PI_33;
+	volatile uint32_t DENALI_PI_34;
+	volatile uint32_t DENALI_PI_35;
+	volatile uint32_t DENALI_PI_36;
+	volatile uint32_t DENALI_PI_37;
+	volatile uint32_t DENALI_PI_38;
+	volatile uint32_t DENALI_PI_39;
+	volatile uint32_t DENALI_PI_40;
+	volatile uint32_t DENALI_PI_41;
+	volatile uint32_t DENALI_PI_42;
+	volatile uint32_t DENALI_PI_43;
+	volatile uint32_t DENALI_PI_44;
+	volatile uint32_t DENALI_PI_45;
+	volatile uint32_t DENALI_PI_46;
+	volatile uint32_t DENALI_PI_47;
+	volatile uint32_t DENALI_PI_48;
+	volatile uint32_t DENALI_PI_49;
+	volatile uint32_t DENALI_PI_50;
+	volatile uint32_t DENALI_PI_51;
+	volatile uint32_t DENALI_PI_52;
+	volatile uint32_t DENALI_PI_53;
+	volatile uint32_t DENALI_PI_54;
+	volatile uint32_t DENALI_PI_55;
+	volatile uint32_t DENALI_PI_56;
+	volatile uint32_t DENALI_PI_57;
+	volatile uint32_t DENALI_PI_58;
+	volatile uint32_t DENALI_PI_59;
+	volatile uint32_t DENALI_PI_60;
+	volatile uint32_t DENALI_PI_61;
+	volatile uint32_t DENALI_PI_62;
+	volatile uint32_t DENALI_PI_63;
+	volatile uint32_t DENALI_PI_64;
+	volatile uint32_t DENALI_PI_65;
+	volatile uint32_t DENALI_PI_66;
+	volatile uint32_t DENALI_PI_67;
+	volatile uint32_t DENALI_PI_68;
+	volatile uint32_t DENALI_PI_69;
+	volatile uint32_t DENALI_PI_70;
+	volatile uint32_t DENALI_PI_71;
+	volatile uint32_t DENALI_PI_72;
+	volatile uint32_t DENALI_PI_73;
+	volatile uint32_t DENALI_PI_74;
+	volatile uint32_t DENALI_PI_75;
+	volatile uint32_t DENALI_PI_76;
+	volatile uint32_t DENALI_PI_77;
+	volatile uint32_t DENALI_PI_78;
+	volatile uint32_t DENALI_PI_79;
+	volatile uint32_t DENALI_PI_80;
+	volatile uint32_t DENALI_PI_81;
+	volatile uint32_t DENALI_PI_82;
+	volatile uint32_t DENALI_PI_83;
+	volatile uint32_t DENALI_PI_84;
+	volatile uint32_t DENALI_PI_85;
+	volatile uint32_t DENALI_PI_86;
+	volatile uint32_t DENALI_PI_87;
+	volatile uint32_t DENALI_PI_88;
+	volatile uint32_t DENALI_PI_89;
+	volatile uint32_t DENALI_PI_90;
+	volatile uint32_t DENALI_PI_91;
+	volatile uint32_t DENALI_PI_92;
+	volatile uint32_t DENALI_PI_93;
+	volatile uint32_t DENALI_PI_94;
+	volatile uint32_t DENALI_PI_95;
+	volatile uint32_t DENALI_PI_96;
+	volatile uint32_t DENALI_PI_97;
+	volatile uint32_t DENALI_PI_98;
+	volatile uint32_t DENALI_PI_99;
+	volatile uint32_t DENALI_PI_100;
+	volatile uint32_t DENALI_PI_101;
+	volatile uint32_t DENALI_PI_102;
+	volatile uint32_t DENALI_PI_103;
+	volatile uint32_t DENALI_PI_104;
+	volatile uint32_t DENALI_PI_105;
+	volatile uint32_t DENALI_PI_106;
+	volatile uint32_t DENALI_PI_107;
+	volatile uint32_t DENALI_PI_108;
+	volatile uint32_t DENALI_PI_109;
+	volatile uint32_t DENALI_PI_110;
+	volatile uint32_t DENALI_PI_111;
+	volatile uint32_t DENALI_PI_112;
+	volatile uint32_t DENALI_PI_113;
+	volatile uint32_t DENALI_PI_114;
+	volatile uint32_t DENALI_PI_115;
+	volatile uint32_t DENALI_PI_116;
+	volatile uint32_t DENALI_PI_117;
+	volatile uint32_t DENALI_PI_118;
+	volatile uint32_t DENALI_PI_119;
+	volatile uint32_t DENALI_PI_120;
+	volatile uint32_t DENALI_PI_121;
+	volatile uint32_t DENALI_PI_122;
+	volatile uint32_t DENALI_PI_123;
+	volatile uint32_t DENALI_PI_124;
+	volatile uint32_t DENALI_PI_125;
+	volatile uint32_t DENALI_PI_126;
+	volatile uint32_t DENALI_PI_127;
+	volatile uint32_t DENALI_PI_128;
+	volatile uint32_t DENALI_PI_129;
+	volatile uint32_t DENALI_PI_130;
+	volatile uint32_t DENALI_PI_131;
+	volatile uint32_t DENALI_PI_132;
+	volatile uint32_t DENALI_PI_133;
+	volatile uint32_t DENALI_PI_134;
+	volatile uint32_t DENALI_PI_135;
+	volatile uint32_t DENALI_PI_136;
+	volatile uint32_t DENALI_PI_137;
+	volatile uint32_t DENALI_PI_138;
+	volatile uint32_t DENALI_PI_139;
+	volatile uint32_t DENALI_PI_140;
+	volatile uint32_t DENALI_PI_141;
+	volatile uint32_t DENALI_PI_142;
+	volatile uint32_t DENALI_PI_143;
+	volatile uint32_t DENALI_PI_144;
+	volatile uint32_t DENALI_PI_145;
+	volatile uint32_t DENALI_PI_146;
+	volatile uint32_t DENALI_PI_147;
+	volatile uint32_t DENALI_PI_148;
+	volatile uint32_t DENALI_PI_149;
+	volatile uint32_t DENALI_PI_150;
+	volatile uint32_t DENALI_PI_151;
+	volatile uint32_t DENALI_PI_152;
+	volatile uint32_t DENALI_PI_153;
+	volatile uint32_t DENALI_PI_154;
+	volatile uint32_t DENALI_PI_155;
+	volatile uint32_t DENALI_PI_156;
+	volatile uint32_t DENALI_PI_157;
+	volatile uint32_t DENALI_PI_158;
+	volatile uint32_t DENALI_PI_159;
+	volatile uint32_t DENALI_PI_160;
+	volatile uint32_t DENALI_PI_161;
+	volatile uint32_t DENALI_PI_162;
+	volatile uint32_t DENALI_PI_163;
+	volatile uint32_t DENALI_PI_164;
+	volatile uint32_t DENALI_PI_165;
+	volatile uint32_t DENALI_PI_166;
+	volatile uint32_t DENALI_PI_167;
+	volatile uint32_t DENALI_PI_168;
+	volatile uint32_t DENALI_PI_169;
+	volatile uint32_t DENALI_PI_170;
+	volatile uint32_t DENALI_PI_171;
+	volatile uint32_t DENALI_PI_172;
+	volatile uint32_t DENALI_PI_173;
+	volatile uint32_t DENALI_PI_174;
+	volatile uint32_t DENALI_PI_175;
+	volatile uint32_t DENALI_PI_176;
+	volatile uint32_t DENALI_PI_177;
+	volatile uint32_t DENALI_PI_178;
+	volatile uint32_t DENALI_PI_179;
+	volatile uint32_t DENALI_PI_180;
+	volatile uint32_t DENALI_PI_181;
+	volatile uint32_t DENALI_PI_182;
+	volatile uint32_t DENALI_PI_183;
+	volatile uint32_t DENALI_PI_184;
+	volatile uint32_t DENALI_PI_185;
+	volatile uint32_t DENALI_PI_186;
+	volatile uint32_t DENALI_PI_187;
+	volatile uint32_t DENALI_PI_188;
+	volatile uint32_t DENALI_PI_189;
+	volatile uint32_t DENALI_PI_190;
+	volatile uint32_t DENALI_PI_191;
+	volatile uint32_t DENALI_PI_192;
+	volatile uint32_t DENALI_PI_193;
+	volatile uint32_t DENALI_PI_194;
+	volatile uint32_t DENALI_PI_195;
+	volatile uint32_t DENALI_PI_196;
+	volatile uint32_t DENALI_PI_197;
+	volatile uint32_t DENALI_PI_198;
+	volatile uint32_t DENALI_PI_199;
+	volatile uint32_t DENALI_PI_200;
+	volatile uint32_t DENALI_PI_201;
+	volatile uint32_t DENALI_PI_202;
+	volatile uint32_t DENALI_PI_203;
+	volatile uint32_t DENALI_PI_204;
+	volatile uint32_t DENALI_PI_205;
+	volatile uint32_t DENALI_PI_206;
+	volatile uint32_t DENALI_PI_207;
+	volatile uint32_t DENALI_PI_208;
+	volatile uint32_t DENALI_PI_209;
+	volatile uint32_t DENALI_PI_210;
+	volatile uint32_t DENALI_PI_211;
+	volatile uint32_t DENALI_PI_212;
+	volatile uint32_t DENALI_PI_213;
+	volatile uint32_t DENALI_PI_214;
+	volatile uint32_t DENALI_PI_215;
+	volatile uint32_t DENALI_PI_216;
+	volatile uint32_t DENALI_PI_217;
+	volatile uint32_t DENALI_PI_218;
+	volatile uint32_t DENALI_PI_219;
+	volatile uint32_t DENALI_PI_220;
+	volatile uint32_t DENALI_PI_221;
+	volatile uint32_t DENALI_PI_222;
+	volatile uint32_t DENALI_PI_223;
+	volatile uint32_t DENALI_PI_224;
+	volatile uint32_t DENALI_PI_225;
+	volatile uint32_t DENALI_PI_226;
+	volatile uint32_t DENALI_PI_227;
+	volatile uint32_t DENALI_PI_228;
+	volatile uint32_t DENALI_PI_229;
+	volatile uint32_t DENALI_PI_230;
+	volatile uint32_t DENALI_PI_231;
+	volatile uint32_t DENALI_PI_232;
+	volatile uint32_t DENALI_PI_233;
+	volatile uint32_t DENALI_PI_234;
+	volatile uint32_t DENALI_PI_235;
+	volatile uint32_t DENALI_PI_236;
+	volatile uint32_t DENALI_PI_237;
+	volatile uint32_t DENALI_PI_238;
+	volatile uint32_t DENALI_PI_239;
+	volatile uint32_t DENALI_PI_240;
+	volatile uint32_t DENALI_PI_241;
+	volatile uint32_t DENALI_PI_242;
+	volatile uint32_t DENALI_PI_243;
+	volatile uint32_t DENALI_PI_244;
+	volatile uint32_t DENALI_PI_245;
+	volatile uint32_t DENALI_PI_246;
+	volatile uint32_t DENALI_PI_247;
+	volatile uint32_t DENALI_PI_248;
+	volatile uint32_t DENALI_PI_249;
+	volatile uint32_t DENALI_PI_250;
+	volatile uint32_t DENALI_PI_251;
+	volatile uint32_t DENALI_PI_252;
+	volatile uint32_t DENALI_PI_253;
+	volatile uint32_t DENALI_PI_254;
+	volatile uint32_t DENALI_PI_255;
+	volatile uint32_t DENALI_PI_256;
+	volatile uint32_t DENALI_PI_257;
+	volatile uint32_t DENALI_PI_258;
+	volatile uint32_t DENALI_PI_259;
+	volatile uint32_t DENALI_PI_260;
+	volatile uint32_t DENALI_PI_261;
+	volatile uint32_t DENALI_PI_262;
+	volatile uint32_t DENALI_PI_263;
+	volatile uint32_t DENALI_PI_264;
+	volatile uint32_t DENALI_PI_265;
+	volatile uint32_t DENALI_PI_266;
+	volatile uint32_t DENALI_PI_267;
+	volatile uint32_t DENALI_PI_268;
+	volatile uint32_t DENALI_PI_269;
+	volatile uint32_t DENALI_PI_270;
+	volatile uint32_t DENALI_PI_271;
+	volatile uint32_t DENALI_PI_272;
+	volatile uint32_t DENALI_PI_273;
+	volatile uint32_t DENALI_PI_274;
+	volatile uint32_t DENALI_PI_275;
+	volatile uint32_t DENALI_PI_276;
+	volatile uint32_t DENALI_PI_277;
+	volatile uint32_t DENALI_PI_278;
+	volatile uint32_t DENALI_PI_279;
+	volatile uint32_t DENALI_PI_280;
+	volatile uint32_t DENALI_PI_281;
+	volatile uint32_t DENALI_PI_282;
+	volatile uint32_t DENALI_PI_283;
+	volatile uint32_t DENALI_PI_284;
+	volatile uint32_t DENALI_PI_285;
+	volatile uint32_t DENALI_PI_286;
+	volatile uint32_t DENALI_PI_287;
+	volatile uint32_t DENALI_PI_288;
+	volatile uint32_t DENALI_PI_289;
+	volatile uint32_t DENALI_PI_290;
+	volatile uint32_t DENALI_PI_291;
+	volatile uint32_t DENALI_PI_292;
+	volatile uint32_t DENALI_PI_293;
+	volatile uint32_t DENALI_PI_294;
+	volatile uint32_t DENALI_PI_295;
+	volatile uint32_t DENALI_PI_296;
+	volatile uint32_t DENALI_PI_297;
+	volatile uint32_t DENALI_PI_298;
+	volatile uint32_t DENALI_PI_299;
+	volatile char pad__1[0x1B50U];
+	volatile uint32_t DENALI_PHY_0;
+	volatile uint32_t DENALI_PHY_1;
+	volatile uint32_t DENALI_PHY_2;
+	volatile uint32_t DENALI_PHY_3;
+	volatile uint32_t DENALI_PHY_4;
+	volatile uint32_t DENALI_PHY_5;
+	volatile uint32_t DENALI_PHY_6;
+	volatile uint32_t DENALI_PHY_7;
+	volatile uint32_t DENALI_PHY_8;
+	volatile uint32_t DENALI_PHY_9;
+	volatile uint32_t DENALI_PHY_10;
+	volatile uint32_t DENALI_PHY_11;
+	volatile uint32_t DENALI_PHY_12;
+	volatile uint32_t DENALI_PHY_13;
+	volatile uint32_t DENALI_PHY_14;
+	volatile uint32_t DENALI_PHY_15;
+	volatile uint32_t DENALI_PHY_16;
+	volatile uint32_t DENALI_PHY_17;
+	volatile uint32_t DENALI_PHY_18;
+	volatile uint32_t DENALI_PHY_19;
+	volatile uint32_t DENALI_PHY_20;
+	volatile uint32_t DENALI_PHY_21;
+	volatile uint32_t DENALI_PHY_22;
+	volatile uint32_t DENALI_PHY_23;
+	volatile uint32_t DENALI_PHY_24;
+	volatile uint32_t DENALI_PHY_25;
+	volatile uint32_t DENALI_PHY_26;
+	volatile uint32_t DENALI_PHY_27;
+	volatile uint32_t DENALI_PHY_28;
+	volatile uint32_t DENALI_PHY_29;
+	volatile uint32_t DENALI_PHY_30;
+	volatile uint32_t DENALI_PHY_31;
+	volatile uint32_t DENALI_PHY_32;
+	volatile uint32_t DENALI_PHY_33;
+	volatile uint32_t DENALI_PHY_34;
+	volatile uint32_t DENALI_PHY_35;
+	volatile uint32_t DENALI_PHY_36;
+	volatile uint32_t DENALI_PHY_37;
+	volatile uint32_t DENALI_PHY_38;
+	volatile uint32_t DENALI_PHY_39;
+	volatile uint32_t DENALI_PHY_40;
+	volatile uint32_t DENALI_PHY_41;
+	volatile uint32_t DENALI_PHY_42;
+	volatile uint32_t DENALI_PHY_43;
+	volatile uint32_t DENALI_PHY_44;
+	volatile uint32_t DENALI_PHY_45;
+	volatile uint32_t DENALI_PHY_46;
+	volatile uint32_t DENALI_PHY_47;
+	volatile uint32_t DENALI_PHY_48;
+	volatile uint32_t DENALI_PHY_49;
+	volatile uint32_t DENALI_PHY_50;
+	volatile uint32_t DENALI_PHY_51;
+	volatile uint32_t DENALI_PHY_52;
+	volatile uint32_t DENALI_PHY_53;
+	volatile uint32_t DENALI_PHY_54;
+	volatile uint32_t DENALI_PHY_55;
+	volatile uint32_t DENALI_PHY_56;
+	volatile uint32_t DENALI_PHY_57;
+	volatile uint32_t DENALI_PHY_58;
+	volatile uint32_t DENALI_PHY_59;
+	volatile uint32_t DENALI_PHY_60;
+	volatile uint32_t DENALI_PHY_61;
+	volatile uint32_t DENALI_PHY_62;
+	volatile uint32_t DENALI_PHY_63;
+	volatile uint32_t DENALI_PHY_64;
+	volatile uint32_t DENALI_PHY_65;
+	volatile uint32_t DENALI_PHY_66;
+	volatile uint32_t DENALI_PHY_67;
+	volatile uint32_t DENALI_PHY_68;
+	volatile uint32_t DENALI_PHY_69;
+	volatile uint32_t DENALI_PHY_70;
+	volatile uint32_t DENALI_PHY_71;
+	volatile uint32_t DENALI_PHY_72;
+	volatile uint32_t DENALI_PHY_73;
+	volatile uint32_t DENALI_PHY_74;
+	volatile uint32_t DENALI_PHY_75;
+	volatile uint32_t DENALI_PHY_76;
+	volatile uint32_t DENALI_PHY_77;
+	volatile uint32_t DENALI_PHY_78;
+	volatile uint32_t DENALI_PHY_79;
+	volatile uint32_t DENALI_PHY_80;
+	volatile uint32_t DENALI_PHY_81;
+	volatile uint32_t DENALI_PHY_82;
+	volatile uint32_t DENALI_PHY_83;
+	volatile uint32_t DENALI_PHY_84;
+	volatile uint32_t DENALI_PHY_85;
+	volatile uint32_t DENALI_PHY_86;
+	volatile uint32_t DENALI_PHY_87;
+	volatile uint32_t DENALI_PHY_88;
+	volatile uint32_t DENALI_PHY_89;
+	volatile uint32_t DENALI_PHY_90;
+	volatile uint32_t DENALI_PHY_91;
+	volatile uint32_t DENALI_PHY_92;
+	volatile uint32_t DENALI_PHY_93;
+	volatile uint32_t DENALI_PHY_94;
+	volatile uint32_t DENALI_PHY_95;
+	volatile uint32_t DENALI_PHY_96;
+	volatile uint32_t DENALI_PHY_97;
+	volatile uint32_t DENALI_PHY_98;
+	volatile uint32_t DENALI_PHY_99;
+	volatile uint32_t DENALI_PHY_100;
+	volatile uint32_t DENALI_PHY_101;
+	volatile uint32_t DENALI_PHY_102;
+	volatile uint32_t DENALI_PHY_103;
+	volatile uint32_t DENALI_PHY_104;
+	volatile uint32_t DENALI_PHY_105;
+	volatile uint32_t DENALI_PHY_106;
+	volatile uint32_t DENALI_PHY_107;
+	volatile uint32_t DENALI_PHY_108;
+	volatile uint32_t DENALI_PHY_109;
+	volatile uint32_t DENALI_PHY_110;
+	volatile uint32_t DENALI_PHY_111;
+	volatile uint32_t DENALI_PHY_112;
+	volatile uint32_t DENALI_PHY_113;
+	volatile uint32_t DENALI_PHY_114;
+	volatile uint32_t DENALI_PHY_115;
+	volatile uint32_t DENALI_PHY_116;
+	volatile uint32_t DENALI_PHY_117;
+	volatile uint32_t DENALI_PHY_118;
+	volatile uint32_t DENALI_PHY_119;
+	volatile uint32_t DENALI_PHY_120;
+	volatile uint32_t DENALI_PHY_121;
+	volatile uint32_t DENALI_PHY_122;
+	volatile uint32_t DENALI_PHY_123;
+	volatile uint32_t DENALI_PHY_124;
+	volatile uint32_t DENALI_PHY_125;
+	volatile uint32_t DENALI_PHY_126;
+	volatile uint32_t DENALI_PHY_127;
+	volatile uint32_t DENALI_PHY_128;
+	volatile uint32_t DENALI_PHY_129;
+	volatile uint32_t DENALI_PHY_130;
+	volatile uint32_t DENALI_PHY_131;
+	volatile uint32_t DENALI_PHY_132;
+	volatile uint32_t DENALI_PHY_133;
+	volatile uint32_t DENALI_PHY_134;
+	volatile uint32_t DENALI_PHY_135;
+	volatile uint32_t DENALI_PHY_136;
+	volatile uint32_t DENALI_PHY_137;
+	volatile uint32_t DENALI_PHY_138;
+	volatile uint32_t DENALI_PHY_139;
+	volatile char pad__2[0x1D0U];
+	volatile uint32_t DENALI_PHY_256;
+	volatile uint32_t DENALI_PHY_257;
+	volatile uint32_t DENALI_PHY_258;
+	volatile uint32_t DENALI_PHY_259;
+	volatile uint32_t DENALI_PHY_260;
+	volatile uint32_t DENALI_PHY_261;
+	volatile uint32_t DENALI_PHY_262;
+	volatile uint32_t DENALI_PHY_263;
+	volatile uint32_t DENALI_PHY_264;
+	volatile uint32_t DENALI_PHY_265;
+	volatile uint32_t DENALI_PHY_266;
+	volatile uint32_t DENALI_PHY_267;
+	volatile uint32_t DENALI_PHY_268;
+	volatile uint32_t DENALI_PHY_269;
+	volatile uint32_t DENALI_PHY_270;
+	volatile uint32_t DENALI_PHY_271;
+	volatile uint32_t DENALI_PHY_272;
+	volatile uint32_t DENALI_PHY_273;
+	volatile uint32_t DENALI_PHY_274;
+	volatile uint32_t DENALI_PHY_275;
+	volatile uint32_t DENALI_PHY_276;
+	volatile uint32_t DENALI_PHY_277;
+	volatile uint32_t DENALI_PHY_278;
+	volatile uint32_t DENALI_PHY_279;
+	volatile uint32_t DENALI_PHY_280;
+	volatile uint32_t DENALI_PHY_281;
+	volatile uint32_t DENALI_PHY_282;
+	volatile uint32_t DENALI_PHY_283;
+	volatile uint32_t DENALI_PHY_284;
+	volatile uint32_t DENALI_PHY_285;
+	volatile uint32_t DENALI_PHY_286;
+	volatile uint32_t DENALI_PHY_287;
+	volatile uint32_t DENALI_PHY_288;
+	volatile uint32_t DENALI_PHY_289;
+	volatile uint32_t DENALI_PHY_290;
+	volatile uint32_t DENALI_PHY_291;
+	volatile uint32_t DENALI_PHY_292;
+	volatile uint32_t DENALI_PHY_293;
+	volatile uint32_t DENALI_PHY_294;
+	volatile uint32_t DENALI_PHY_295;
+	volatile uint32_t DENALI_PHY_296;
+	volatile uint32_t DENALI_PHY_297;
+	volatile uint32_t DENALI_PHY_298;
+	volatile uint32_t DENALI_PHY_299;
+	volatile uint32_t DENALI_PHY_300;
+	volatile uint32_t DENALI_PHY_301;
+	volatile uint32_t DENALI_PHY_302;
+	volatile uint32_t DENALI_PHY_303;
+	volatile uint32_t DENALI_PHY_304;
+	volatile uint32_t DENALI_PHY_305;
+	volatile uint32_t DENALI_PHY_306;
+	volatile uint32_t DENALI_PHY_307;
+	volatile uint32_t DENALI_PHY_308;
+	volatile uint32_t DENALI_PHY_309;
+	volatile uint32_t DENALI_PHY_310;
+	volatile uint32_t DENALI_PHY_311;
+	volatile uint32_t DENALI_PHY_312;
+	volatile uint32_t DENALI_PHY_313;
+	volatile uint32_t DENALI_PHY_314;
+	volatile uint32_t DENALI_PHY_315;
+	volatile uint32_t DENALI_PHY_316;
+	volatile uint32_t DENALI_PHY_317;
+	volatile uint32_t DENALI_PHY_318;
+	volatile uint32_t DENALI_PHY_319;
+	volatile uint32_t DENALI_PHY_320;
+	volatile uint32_t DENALI_PHY_321;
+	volatile uint32_t DENALI_PHY_322;
+	volatile uint32_t DENALI_PHY_323;
+	volatile uint32_t DENALI_PHY_324;
+	volatile uint32_t DENALI_PHY_325;
+	volatile uint32_t DENALI_PHY_326;
+	volatile uint32_t DENALI_PHY_327;
+	volatile uint32_t DENALI_PHY_328;
+	volatile uint32_t DENALI_PHY_329;
+	volatile uint32_t DENALI_PHY_330;
+	volatile uint32_t DENALI_PHY_331;
+	volatile uint32_t DENALI_PHY_332;
+	volatile uint32_t DENALI_PHY_333;
+	volatile uint32_t DENALI_PHY_334;
+	volatile uint32_t DENALI_PHY_335;
+	volatile uint32_t DENALI_PHY_336;
+	volatile uint32_t DENALI_PHY_337;
+	volatile uint32_t DENALI_PHY_338;
+	volatile uint32_t DENALI_PHY_339;
+	volatile uint32_t DENALI_PHY_340;
+	volatile uint32_t DENALI_PHY_341;
+	volatile uint32_t DENALI_PHY_342;
+	volatile uint32_t DENALI_PHY_343;
+	volatile uint32_t DENALI_PHY_344;
+	volatile uint32_t DENALI_PHY_345;
+	volatile uint32_t DENALI_PHY_346;
+	volatile uint32_t DENALI_PHY_347;
+	volatile uint32_t DENALI_PHY_348;
+	volatile uint32_t DENALI_PHY_349;
+	volatile uint32_t DENALI_PHY_350;
+	volatile uint32_t DENALI_PHY_351;
+	volatile uint32_t DENALI_PHY_352;
+	volatile uint32_t DENALI_PHY_353;
+	volatile uint32_t DENALI_PHY_354;
+	volatile uint32_t DENALI_PHY_355;
+	volatile uint32_t DENALI_PHY_356;
+	volatile uint32_t DENALI_PHY_357;
+	volatile uint32_t DENALI_PHY_358;
+	volatile uint32_t DENALI_PHY_359;
+	volatile uint32_t DENALI_PHY_360;
+	volatile uint32_t DENALI_PHY_361;
+	volatile uint32_t DENALI_PHY_362;
+	volatile uint32_t DENALI_PHY_363;
+	volatile uint32_t DENALI_PHY_364;
+	volatile uint32_t DENALI_PHY_365;
+	volatile uint32_t DENALI_PHY_366;
+	volatile uint32_t DENALI_PHY_367;
+	volatile uint32_t DENALI_PHY_368;
+	volatile uint32_t DENALI_PHY_369;
+	volatile uint32_t DENALI_PHY_370;
+	volatile uint32_t DENALI_PHY_371;
+	volatile uint32_t DENALI_PHY_372;
+	volatile uint32_t DENALI_PHY_373;
+	volatile uint32_t DENALI_PHY_374;
+	volatile uint32_t DENALI_PHY_375;
+	volatile uint32_t DENALI_PHY_376;
+	volatile uint32_t DENALI_PHY_377;
+	volatile uint32_t DENALI_PHY_378;
+	volatile uint32_t DENALI_PHY_379;
+	volatile uint32_t DENALI_PHY_380;
+	volatile uint32_t DENALI_PHY_381;
+	volatile uint32_t DENALI_PHY_382;
+	volatile uint32_t DENALI_PHY_383;
+	volatile uint32_t DENALI_PHY_384;
+	volatile uint32_t DENALI_PHY_385;
+	volatile uint32_t DENALI_PHY_386;
+	volatile uint32_t DENALI_PHY_387;
+	volatile uint32_t DENALI_PHY_388;
+	volatile uint32_t DENALI_PHY_389;
+	volatile uint32_t DENALI_PHY_390;
+	volatile uint32_t DENALI_PHY_391;
+	volatile uint32_t DENALI_PHY_392;
+	volatile uint32_t DENALI_PHY_393;
+	volatile uint32_t DENALI_PHY_394;
+	volatile uint32_t DENALI_PHY_395;
+	volatile char pad__3[0x1D0U];
+	volatile uint32_t DENALI_PHY_512;
+	volatile uint32_t DENALI_PHY_513;
+	volatile uint32_t DENALI_PHY_514;
+	volatile uint32_t DENALI_PHY_515;
+	volatile uint32_t DENALI_PHY_516;
+	volatile uint32_t DENALI_PHY_517;
+	volatile uint32_t DENALI_PHY_518;
+	volatile uint32_t DENALI_PHY_519;
+	volatile uint32_t DENALI_PHY_520;
+	volatile uint32_t DENALI_PHY_521;
+	volatile uint32_t DENALI_PHY_522;
+	volatile uint32_t DENALI_PHY_523;
+	volatile uint32_t DENALI_PHY_524;
+	volatile uint32_t DENALI_PHY_525;
+	volatile uint32_t DENALI_PHY_526;
+	volatile uint32_t DENALI_PHY_527;
+	volatile uint32_t DENALI_PHY_528;
+	volatile uint32_t DENALI_PHY_529;
+	volatile uint32_t DENALI_PHY_530;
+	volatile uint32_t DENALI_PHY_531;
+	volatile uint32_t DENALI_PHY_532;
+	volatile uint32_t DENALI_PHY_533;
+	volatile uint32_t DENALI_PHY_534;
+	volatile uint32_t DENALI_PHY_535;
+	volatile uint32_t DENALI_PHY_536;
+	volatile uint32_t DENALI_PHY_537;
+	volatile uint32_t DENALI_PHY_538;
+	volatile uint32_t DENALI_PHY_539;
+	volatile uint32_t DENALI_PHY_540;
+	volatile uint32_t DENALI_PHY_541;
+	volatile uint32_t DENALI_PHY_542;
+	volatile uint32_t DENALI_PHY_543;
+	volatile uint32_t DENALI_PHY_544;
+	volatile uint32_t DENALI_PHY_545;
+	volatile uint32_t DENALI_PHY_546;
+	volatile uint32_t DENALI_PHY_547;
+	volatile uint32_t DENALI_PHY_548;
+	volatile uint32_t DENALI_PHY_549;
+	volatile uint32_t DENALI_PHY_550;
+	volatile uint32_t DENALI_PHY_551;
+	volatile uint32_t DENALI_PHY_552;
+	volatile uint32_t DENALI_PHY_553;
+	volatile uint32_t DENALI_PHY_554;
+	volatile uint32_t DENALI_PHY_555;
+	volatile uint32_t DENALI_PHY_556;
+	volatile uint32_t DENALI_PHY_557;
+	volatile uint32_t DENALI_PHY_558;
+	volatile uint32_t DENALI_PHY_559;
+	volatile uint32_t DENALI_PHY_560;
+	volatile uint32_t DENALI_PHY_561;
+	volatile uint32_t DENALI_PHY_562;
+	volatile uint32_t DENALI_PHY_563;
+	volatile uint32_t DENALI_PHY_564;
+	volatile uint32_t DENALI_PHY_565;
+	volatile uint32_t DENALI_PHY_566;
+	volatile uint32_t DENALI_PHY_567;
+	volatile uint32_t DENALI_PHY_568;
+	volatile uint32_t DENALI_PHY_569;
+	volatile uint32_t DENALI_PHY_570;
+	volatile uint32_t DENALI_PHY_571;
+	volatile uint32_t DENALI_PHY_572;
+	volatile uint32_t DENALI_PHY_573;
+	volatile uint32_t DENALI_PHY_574;
+	volatile uint32_t DENALI_PHY_575;
+	volatile uint32_t DENALI_PHY_576;
+	volatile uint32_t DENALI_PHY_577;
+	volatile uint32_t DENALI_PHY_578;
+	volatile uint32_t DENALI_PHY_579;
+	volatile uint32_t DENALI_PHY_580;
+	volatile uint32_t DENALI_PHY_581;
+	volatile uint32_t DENALI_PHY_582;
+	volatile uint32_t DENALI_PHY_583;
+	volatile uint32_t DENALI_PHY_584;
+	volatile uint32_t DENALI_PHY_585;
+	volatile uint32_t DENALI_PHY_586;
+	volatile uint32_t DENALI_PHY_587;
+	volatile uint32_t DENALI_PHY_588;
+	volatile uint32_t DENALI_PHY_589;
+	volatile uint32_t DENALI_PHY_590;
+	volatile uint32_t DENALI_PHY_591;
+	volatile uint32_t DENALI_PHY_592;
+	volatile uint32_t DENALI_PHY_593;
+	volatile uint32_t DENALI_PHY_594;
+	volatile uint32_t DENALI_PHY_595;
+	volatile uint32_t DENALI_PHY_596;
+	volatile uint32_t DENALI_PHY_597;
+	volatile uint32_t DENALI_PHY_598;
+	volatile uint32_t DENALI_PHY_599;
+	volatile uint32_t DENALI_PHY_600;
+	volatile uint32_t DENALI_PHY_601;
+	volatile uint32_t DENALI_PHY_602;
+	volatile uint32_t DENALI_PHY_603;
+	volatile uint32_t DENALI_PHY_604;
+	volatile uint32_t DENALI_PHY_605;
+	volatile uint32_t DENALI_PHY_606;
+	volatile uint32_t DENALI_PHY_607;
+	volatile uint32_t DENALI_PHY_608;
+	volatile uint32_t DENALI_PHY_609;
+	volatile uint32_t DENALI_PHY_610;
+	volatile uint32_t DENALI_PHY_611;
+	volatile uint32_t DENALI_PHY_612;
+	volatile uint32_t DENALI_PHY_613;
+	volatile uint32_t DENALI_PHY_614;
+	volatile uint32_t DENALI_PHY_615;
+	volatile uint32_t DENALI_PHY_616;
+	volatile uint32_t DENALI_PHY_617;
+	volatile uint32_t DENALI_PHY_618;
+	volatile uint32_t DENALI_PHY_619;
+	volatile uint32_t DENALI_PHY_620;
+	volatile uint32_t DENALI_PHY_621;
+	volatile uint32_t DENALI_PHY_622;
+	volatile uint32_t DENALI_PHY_623;
+	volatile uint32_t DENALI_PHY_624;
+	volatile uint32_t DENALI_PHY_625;
+	volatile uint32_t DENALI_PHY_626;
+	volatile uint32_t DENALI_PHY_627;
+	volatile uint32_t DENALI_PHY_628;
+	volatile uint32_t DENALI_PHY_629;
+	volatile uint32_t DENALI_PHY_630;
+	volatile uint32_t DENALI_PHY_631;
+	volatile uint32_t DENALI_PHY_632;
+	volatile uint32_t DENALI_PHY_633;
+	volatile uint32_t DENALI_PHY_634;
+	volatile uint32_t DENALI_PHY_635;
+	volatile uint32_t DENALI_PHY_636;
+	volatile uint32_t DENALI_PHY_637;
+	volatile uint32_t DENALI_PHY_638;
+	volatile uint32_t DENALI_PHY_639;
+	volatile uint32_t DENALI_PHY_640;
+	volatile uint32_t DENALI_PHY_641;
+	volatile uint32_t DENALI_PHY_642;
+	volatile uint32_t DENALI_PHY_643;
+	volatile uint32_t DENALI_PHY_644;
+	volatile uint32_t DENALI_PHY_645;
+	volatile uint32_t DENALI_PHY_646;
+	volatile uint32_t DENALI_PHY_647;
+	volatile uint32_t DENALI_PHY_648;
+	volatile uint32_t DENALI_PHY_649;
+	volatile uint32_t DENALI_PHY_650;
+	volatile uint32_t DENALI_PHY_651;
+	volatile char pad__4[0x1D0U];
+	volatile uint32_t DENALI_PHY_768;
+	volatile uint32_t DENALI_PHY_769;
+	volatile uint32_t DENALI_PHY_770;
+	volatile uint32_t DENALI_PHY_771;
+	volatile uint32_t DENALI_PHY_772;
+	volatile uint32_t DENALI_PHY_773;
+	volatile uint32_t DENALI_PHY_774;
+	volatile uint32_t DENALI_PHY_775;
+	volatile uint32_t DENALI_PHY_776;
+	volatile uint32_t DENALI_PHY_777;
+	volatile uint32_t DENALI_PHY_778;
+	volatile uint32_t DENALI_PHY_779;
+	volatile uint32_t DENALI_PHY_780;
+	volatile uint32_t DENALI_PHY_781;
+	volatile uint32_t DENALI_PHY_782;
+	volatile uint32_t DENALI_PHY_783;
+	volatile uint32_t DENALI_PHY_784;
+	volatile uint32_t DENALI_PHY_785;
+	volatile uint32_t DENALI_PHY_786;
+	volatile uint32_t DENALI_PHY_787;
+	volatile uint32_t DENALI_PHY_788;
+	volatile uint32_t DENALI_PHY_789;
+	volatile uint32_t DENALI_PHY_790;
+	volatile uint32_t DENALI_PHY_791;
+	volatile uint32_t DENALI_PHY_792;
+	volatile uint32_t DENALI_PHY_793;
+	volatile uint32_t DENALI_PHY_794;
+	volatile uint32_t DENALI_PHY_795;
+	volatile uint32_t DENALI_PHY_796;
+	volatile uint32_t DENALI_PHY_797;
+	volatile uint32_t DENALI_PHY_798;
+	volatile uint32_t DENALI_PHY_799;
+	volatile uint32_t DENALI_PHY_800;
+	volatile uint32_t DENALI_PHY_801;
+	volatile uint32_t DENALI_PHY_802;
+	volatile uint32_t DENALI_PHY_803;
+	volatile uint32_t DENALI_PHY_804;
+	volatile uint32_t DENALI_PHY_805;
+	volatile uint32_t DENALI_PHY_806;
+	volatile uint32_t DENALI_PHY_807;
+	volatile uint32_t DENALI_PHY_808;
+	volatile uint32_t DENALI_PHY_809;
+	volatile uint32_t DENALI_PHY_810;
+	volatile uint32_t DENALI_PHY_811;
+	volatile uint32_t DENALI_PHY_812;
+	volatile uint32_t DENALI_PHY_813;
+	volatile uint32_t DENALI_PHY_814;
+	volatile uint32_t DENALI_PHY_815;
+	volatile uint32_t DENALI_PHY_816;
+	volatile uint32_t DENALI_PHY_817;
+	volatile uint32_t DENALI_PHY_818;
+	volatile uint32_t DENALI_PHY_819;
+	volatile uint32_t DENALI_PHY_820;
+	volatile uint32_t DENALI_PHY_821;
+	volatile uint32_t DENALI_PHY_822;
+	volatile uint32_t DENALI_PHY_823;
+	volatile uint32_t DENALI_PHY_824;
+	volatile uint32_t DENALI_PHY_825;
+	volatile uint32_t DENALI_PHY_826;
+	volatile uint32_t DENALI_PHY_827;
+	volatile uint32_t DENALI_PHY_828;
+	volatile uint32_t DENALI_PHY_829;
+	volatile uint32_t DENALI_PHY_830;
+	volatile uint32_t DENALI_PHY_831;
+	volatile uint32_t DENALI_PHY_832;
+	volatile uint32_t DENALI_PHY_833;
+	volatile uint32_t DENALI_PHY_834;
+	volatile uint32_t DENALI_PHY_835;
+	volatile uint32_t DENALI_PHY_836;
+	volatile uint32_t DENALI_PHY_837;
+	volatile uint32_t DENALI_PHY_838;
+	volatile uint32_t DENALI_PHY_839;
+	volatile uint32_t DENALI_PHY_840;
+	volatile uint32_t DENALI_PHY_841;
+	volatile uint32_t DENALI_PHY_842;
+	volatile uint32_t DENALI_PHY_843;
+	volatile uint32_t DENALI_PHY_844;
+	volatile uint32_t DENALI_PHY_845;
+	volatile uint32_t DENALI_PHY_846;
+	volatile uint32_t DENALI_PHY_847;
+	volatile uint32_t DENALI_PHY_848;
+	volatile uint32_t DENALI_PHY_849;
+	volatile uint32_t DENALI_PHY_850;
+	volatile uint32_t DENALI_PHY_851;
+	volatile uint32_t DENALI_PHY_852;
+	volatile uint32_t DENALI_PHY_853;
+	volatile uint32_t DENALI_PHY_854;
+	volatile uint32_t DENALI_PHY_855;
+	volatile uint32_t DENALI_PHY_856;
+	volatile uint32_t DENALI_PHY_857;
+	volatile uint32_t DENALI_PHY_858;
+	volatile uint32_t DENALI_PHY_859;
+	volatile uint32_t DENALI_PHY_860;
+	volatile uint32_t DENALI_PHY_861;
+	volatile uint32_t DENALI_PHY_862;
+	volatile uint32_t DENALI_PHY_863;
+	volatile uint32_t DENALI_PHY_864;
+	volatile uint32_t DENALI_PHY_865;
+	volatile uint32_t DENALI_PHY_866;
+	volatile uint32_t DENALI_PHY_867;
+	volatile uint32_t DENALI_PHY_868;
+	volatile uint32_t DENALI_PHY_869;
+	volatile uint32_t DENALI_PHY_870;
+	volatile uint32_t DENALI_PHY_871;
+	volatile uint32_t DENALI_PHY_872;
+	volatile uint32_t DENALI_PHY_873;
+	volatile uint32_t DENALI_PHY_874;
+	volatile uint32_t DENALI_PHY_875;
+	volatile uint32_t DENALI_PHY_876;
+	volatile uint32_t DENALI_PHY_877;
+	volatile uint32_t DENALI_PHY_878;
+	volatile uint32_t DENALI_PHY_879;
+	volatile uint32_t DENALI_PHY_880;
+	volatile uint32_t DENALI_PHY_881;
+	volatile uint32_t DENALI_PHY_882;
+	volatile uint32_t DENALI_PHY_883;
+	volatile uint32_t DENALI_PHY_884;
+	volatile uint32_t DENALI_PHY_885;
+	volatile uint32_t DENALI_PHY_886;
+	volatile uint32_t DENALI_PHY_887;
+	volatile uint32_t DENALI_PHY_888;
+	volatile uint32_t DENALI_PHY_889;
+	volatile uint32_t DENALI_PHY_890;
+	volatile uint32_t DENALI_PHY_891;
+	volatile uint32_t DENALI_PHY_892;
+	volatile uint32_t DENALI_PHY_893;
+	volatile uint32_t DENALI_PHY_894;
+	volatile uint32_t DENALI_PHY_895;
+	volatile uint32_t DENALI_PHY_896;
+	volatile uint32_t DENALI_PHY_897;
+	volatile uint32_t DENALI_PHY_898;
+	volatile uint32_t DENALI_PHY_899;
+	volatile uint32_t DENALI_PHY_900;
+	volatile uint32_t DENALI_PHY_901;
+	volatile uint32_t DENALI_PHY_902;
+	volatile uint32_t DENALI_PHY_903;
+	volatile uint32_t DENALI_PHY_904;
+	volatile uint32_t DENALI_PHY_905;
+	volatile uint32_t DENALI_PHY_906;
+	volatile uint32_t DENALI_PHY_907;
+	volatile char pad__5[0x1D0U];
+	volatile uint32_t DENALI_PHY_1024;
+	volatile uint32_t DENALI_PHY_1025;
+	volatile uint32_t DENALI_PHY_1026;
+	volatile uint32_t DENALI_PHY_1027;
+	volatile uint32_t DENALI_PHY_1028;
+	volatile uint32_t DENALI_PHY_1029;
+	volatile uint32_t DENALI_PHY_1030;
+	volatile uint32_t DENALI_PHY_1031;
+	volatile uint32_t DENALI_PHY_1032;
+	volatile uint32_t DENALI_PHY_1033;
+	volatile uint32_t DENALI_PHY_1034;
+	volatile uint32_t DENALI_PHY_1035;
+	volatile uint32_t DENALI_PHY_1036;
+	volatile uint32_t DENALI_PHY_1037;
+	volatile uint32_t DENALI_PHY_1038;
+	volatile uint32_t DENALI_PHY_1039;
+	volatile uint32_t DENALI_PHY_1040;
+	volatile uint32_t DENALI_PHY_1041;
+	volatile uint32_t DENALI_PHY_1042;
+	volatile uint32_t DENALI_PHY_1043;
+	volatile uint32_t DENALI_PHY_1044;
+	volatile uint32_t DENALI_PHY_1045;
+	volatile uint32_t DENALI_PHY_1046;
+	volatile uint32_t DENALI_PHY_1047;
+	volatile uint32_t DENALI_PHY_1048;
+	volatile uint32_t DENALI_PHY_1049;
+	volatile uint32_t DENALI_PHY_1050;
+	volatile uint32_t DENALI_PHY_1051;
+	volatile uint32_t DENALI_PHY_1052;
+	volatile uint32_t DENALI_PHY_1053;
+	volatile uint32_t DENALI_PHY_1054;
+	volatile uint32_t DENALI_PHY_1055;
+	volatile uint32_t DENALI_PHY_1056;
+	volatile uint32_t DENALI_PHY_1057;
+	volatile uint32_t DENALI_PHY_1058;
+	volatile uint32_t DENALI_PHY_1059;
+	volatile uint32_t DENALI_PHY_1060;
+	volatile uint32_t DENALI_PHY_1061;
+	volatile uint32_t DENALI_PHY_1062;
+	volatile uint32_t DENALI_PHY_1063;
+	volatile uint32_t DENALI_PHY_1064;
+	volatile uint32_t DENALI_PHY_1065;
+	volatile uint32_t DENALI_PHY_1066;
+	volatile uint32_t DENALI_PHY_1067;
+	volatile uint32_t DENALI_PHY_1068;
+	volatile uint32_t DENALI_PHY_1069;
+	volatile uint32_t DENALI_PHY_1070;
+	volatile uint32_t DENALI_PHY_1071;
+	volatile uint32_t DENALI_PHY_1072;
+	volatile uint32_t DENALI_PHY_1073;
+	volatile uint32_t DENALI_PHY_1074;
+	volatile uint32_t DENALI_PHY_1075;
+	volatile char pad__6[0x330U];
+	volatile uint32_t DENALI_PHY_1280;
+	volatile uint32_t DENALI_PHY_1281;
+	volatile uint32_t DENALI_PHY_1282;
+	volatile uint32_t DENALI_PHY_1283;
+	volatile uint32_t DENALI_PHY_1284;
+	volatile uint32_t DENALI_PHY_1285;
+	volatile uint32_t DENALI_PHY_1286;
+	volatile uint32_t DENALI_PHY_1287;
+	volatile uint32_t DENALI_PHY_1288;
+	volatile uint32_t DENALI_PHY_1289;
+	volatile uint32_t DENALI_PHY_1290;
+	volatile uint32_t DENALI_PHY_1291;
+	volatile uint32_t DENALI_PHY_1292;
+	volatile uint32_t DENALI_PHY_1293;
+	volatile uint32_t DENALI_PHY_1294;
+	volatile uint32_t DENALI_PHY_1295;
+	volatile uint32_t DENALI_PHY_1296;
+	volatile uint32_t DENALI_PHY_1297;
+	volatile uint32_t DENALI_PHY_1298;
+	volatile uint32_t DENALI_PHY_1299;
+	volatile uint32_t DENALI_PHY_1300;
+	volatile uint32_t DENALI_PHY_1301;
+	volatile uint32_t DENALI_PHY_1302;
+	volatile uint32_t DENALI_PHY_1303;
+	volatile uint32_t DENALI_PHY_1304;
+	volatile uint32_t DENALI_PHY_1305;
+	volatile uint32_t DENALI_PHY_1306;
+	volatile uint32_t DENALI_PHY_1307;
+	volatile uint32_t DENALI_PHY_1308;
+	volatile uint32_t DENALI_PHY_1309;
+	volatile uint32_t DENALI_PHY_1310;
+	volatile uint32_t DENALI_PHY_1311;
+	volatile uint32_t DENALI_PHY_1312;
+	volatile uint32_t DENALI_PHY_1313;
+	volatile uint32_t DENALI_PHY_1314;
+	volatile uint32_t DENALI_PHY_1315;
+	volatile uint32_t DENALI_PHY_1316;
+	volatile uint32_t DENALI_PHY_1317;
+	volatile uint32_t DENALI_PHY_1318;
+	volatile uint32_t DENALI_PHY_1319;
+	volatile uint32_t DENALI_PHY_1320;
+	volatile uint32_t DENALI_PHY_1321;
+	volatile uint32_t DENALI_PHY_1322;
+	volatile uint32_t DENALI_PHY_1323;
+	volatile uint32_t DENALI_PHY_1324;
+	volatile uint32_t DENALI_PHY_1325;
+	volatile uint32_t DENALI_PHY_1326;
+	volatile uint32_t DENALI_PHY_1327;
+	volatile uint32_t DENALI_PHY_1328;
+	volatile uint32_t DENALI_PHY_1329;
+	volatile uint32_t DENALI_PHY_1330;
+	volatile uint32_t DENALI_PHY_1331;
+	volatile uint32_t DENALI_PHY_1332;
+	volatile uint32_t DENALI_PHY_1333;
+	volatile uint32_t DENALI_PHY_1334;
+	volatile uint32_t DENALI_PHY_1335;
+	volatile uint32_t DENALI_PHY_1336;
+	volatile uint32_t DENALI_PHY_1337;
+	volatile uint32_t DENALI_PHY_1338;
+	volatile uint32_t DENALI_PHY_1339;
+	volatile uint32_t DENALI_PHY_1340;
+	volatile uint32_t DENALI_PHY_1341;
+	volatile uint32_t DENALI_PHY_1342;
+	volatile uint32_t DENALI_PHY_1343;
+	volatile uint32_t DENALI_PHY_1344;
+	volatile uint32_t DENALI_PHY_1345;
+	volatile uint32_t DENALI_PHY_1346;
+	volatile uint32_t DENALI_PHY_1347;
+	volatile uint32_t DENALI_PHY_1348;
+	volatile uint32_t DENALI_PHY_1349;
+	volatile uint32_t DENALI_PHY_1350;
+	volatile uint32_t DENALI_PHY_1351;
+	volatile uint32_t DENALI_PHY_1352;
+	volatile uint32_t DENALI_PHY_1353;
+	volatile uint32_t DENALI_PHY_1354;
+	volatile uint32_t DENALI_PHY_1355;
+	volatile uint32_t DENALI_PHY_1356;
+	volatile uint32_t DENALI_PHY_1357;
+	volatile uint32_t DENALI_PHY_1358;
+	volatile uint32_t DENALI_PHY_1359;
+	volatile uint32_t DENALI_PHY_1360;
+	volatile uint32_t DENALI_PHY_1361;
+	volatile uint32_t DENALI_PHY_1362;
+	volatile uint32_t DENALI_PHY_1363;
+	volatile uint32_t DENALI_PHY_1364;
+	volatile uint32_t DENALI_PHY_1365;
+	volatile uint32_t DENALI_PHY_1366;
+	volatile uint32_t DENALI_PHY_1367;
+	volatile uint32_t DENALI_PHY_1368;
+	volatile uint32_t DENALI_PHY_1369;
+	volatile uint32_t DENALI_PHY_1370;
+	volatile uint32_t DENALI_PHY_1371;
+	volatile uint32_t DENALI_PHY_1372;
+	volatile uint32_t DENALI_PHY_1373;
+	volatile uint32_t DENALI_PHY_1374;
+	volatile uint32_t DENALI_PHY_1375;
+	volatile uint32_t DENALI_PHY_1376;
+	volatile uint32_t DENALI_PHY_1377;
+	volatile uint32_t DENALI_PHY_1378;
+	volatile uint32_t DENALI_PHY_1379;
+	volatile uint32_t DENALI_PHY_1380;
+	volatile uint32_t DENALI_PHY_1381;
+	volatile uint32_t DENALI_PHY_1382;
+	volatile uint32_t DENALI_PHY_1383;
+	volatile uint32_t DENALI_PHY_1384;
+	volatile uint32_t DENALI_PHY_1385;
+	volatile uint32_t DENALI_PHY_1386;
+	volatile uint32_t DENALI_PHY_1387;
+	volatile uint32_t DENALI_PHY_1388;
+	volatile uint32_t DENALI_PHY_1389;
+	volatile uint32_t DENALI_PHY_1390;
+	volatile uint32_t DENALI_PHY_1391;
+	volatile uint32_t DENALI_PHY_1392;
+	volatile uint32_t DENALI_PHY_1393;
+	volatile uint32_t DENALI_PHY_1394;
+	volatile uint32_t DENALI_PHY_1395;
+	volatile uint32_t DENALI_PHY_1396;
+	volatile uint32_t DENALI_PHY_1397;
+	volatile uint32_t DENALI_PHY_1398;
+	volatile uint32_t DENALI_PHY_1399;
+	volatile uint32_t DENALI_PHY_1400;
+	volatile uint32_t DENALI_PHY_1401;
+	volatile uint32_t DENALI_PHY_1402;
+	volatile uint32_t DENALI_PHY_1403;
+	volatile uint32_t DENALI_PHY_1404;
+	volatile uint32_t DENALI_PHY_1405;
+	volatile uint32_t DENALI_PHY_1406;
+	volatile uint32_t DENALI_PHY_1407;
+	volatile uint32_t DENALI_PHY_1408;
+	volatile uint32_t DENALI_PHY_1409;
+	volatile uint32_t DENALI_PHY_1410;
+	volatile uint32_t DENALI_PHY_1411;
+	volatile uint32_t DENALI_PHY_1412;
+	volatile uint32_t DENALI_PHY_1413;
+	volatile uint32_t DENALI_PHY_1414;
+	volatile uint32_t DENALI_PHY_1415;
+	volatile uint32_t DENALI_PHY_1416;
+	volatile uint32_t DENALI_PHY_1417;
+	volatile uint32_t DENALI_PHY_1418;
+	volatile uint32_t DENALI_PHY_1419;
+	volatile uint32_t DENALI_PHY_1420;
+	volatile uint32_t DENALI_PHY_1421;
+	volatile uint32_t DENALI_PHY_1422;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
new file mode 100644
index 0000000000..3208b1cf9d
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2373 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK				               0x000F07FFU
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK				              0x000F07FFU
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK  0x000F0000U
+#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH          4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK				               0x000703FFU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK				              0x000703FFU
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH       10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK   0x00070000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH           3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK				               0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK				              0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK     0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH             2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT				24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET				 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK				               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK				              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK				               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK				              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH				      6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK				               0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK				              0x01030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK               0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH				       6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK              0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH				      4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH				     2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT       24U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET        0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK				               0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK				              0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET               0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH           2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH              5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK				               0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK				              0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH				4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT       8U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH       4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH        2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK   0x1F000000U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH           5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK				               0x0101FF03U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK				              0x0101FF03U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK				0x00000003U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH				        2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK				0x0001FF00U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT				        8U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH				        9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT				24U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET				 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK				               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK  0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH         32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK				              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK     0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH            28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK				              0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK				             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH				 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK          0x0001FF00U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH				  9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK    0x01000000U
+#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET            0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK				              0x007F3F01U
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK				             0x007F3F01U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH       1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR       0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET       0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH              6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK             0x007F0000U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH				     7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK				              0x000F03FFU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_MASK    0x000F0000U
+#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET				   0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK				              0x070101FFU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK				             0x070101FFU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK     0x000001FFU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK				      0x00010000U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT				             16U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH				              1U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR				              0U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET				              0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK				  0x07000000U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT				         24U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH				          3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK				              0x000301FFU
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK				             0x000301FFU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK     0x000001FFU
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH				  2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH				 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK				              0x00000301U
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK				             0x00000301U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH				     1U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR				     0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET				     0U
+#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17
+#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK              0x00000300U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH				      2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH				       32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH				       32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK				              0x070F0107U
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK				             0x070F0107U
+#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK      0x00000007U
+#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH              3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK    0x00000100U
+#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET            0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH         4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK        0x07000000U
+#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH				3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK				              0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH				  4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH				4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH				4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK				              0xFF030001U
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK				             0xFF030001U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH				     1U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR				     0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET				     0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET				  0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK				 0x00030000U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH				         2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK            0xFF000000U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH				    8U
+#define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK				              0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK				             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK          0x0000003FU
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK				    0x00FF0000U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT				           16U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH				            8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK				              0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK				             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH				   10U
+#define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK				              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK				             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK          0x0000003FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK              0x00030000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH				      2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH          5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK				              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH          8U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK            0x0000FF00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH				    8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK           0x3F000000U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH				   6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK				              0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK				             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK				0x00000007U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH				        3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT    8U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH   11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK				              0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK				             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH             4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH         8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET         0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK				              0x000001FFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH				 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK				 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH				        32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK				 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH				        32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK				 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH				        32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK				 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH				        32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK				              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK				 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH				        16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH				     1U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR				     0U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET				     0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK        0x000003FFU
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH               10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_MASK       0x03FF0000U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH              10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK   0x03FF0000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK				              0x00FF0001U
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK				             0x00FF0001U
+#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET           0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH				    6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH				       8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH				   32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK				              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK       0x0000FFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH              16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_MASK        0x07FF0000U
+#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK				              0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK				             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK       0x0000007FU
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH               7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK        0x00FF0000U
+#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH				8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK				              0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK				             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH        11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK				              0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK				             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH          8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH           8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH				       3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK      0x000003FFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK				              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH				  17U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK				              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH				   16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0
+
+#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK      0x3FFF0000U
+#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK				              0x00003FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK      0x00003FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK				              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH				  18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK				              0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK				             0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH     2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH				  32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH				32U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK				              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH				 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH               32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK				              0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK				             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK				   0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH				          31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK				              0x0000003FU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK				             0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK				   0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH				           6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH				      32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH             32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK				              0x010001FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK				             0x010001FFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH            8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET				 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET				    0U
+#define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66
+#define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK            0x01000000U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET				    0U
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK				              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK         0x000000FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH				 8U
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOSET        0U
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK				 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK				              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK				 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK				 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK				              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK				 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK				 0x01FF0000U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK				              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK				 0x000001FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK				 0x01FF0000U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK				              0x000001FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK				 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK				              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK				  0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH				         18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK				              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK				 0x000001FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH				         9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK				              0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK				             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK				 0x000007FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH				        11U
+#define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK            0x01FF0000U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH				    9U
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK				              0x017F7F01U
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK				             0x017F7F01U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH				     1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR				     0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET				     0U
+#define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK           0x00007F00U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH				   7U
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT				16U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH				 7U
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK            0x01000000U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET				    0U
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK				              0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK				             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH				 12U
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK             0x07FF0000U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH				    11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK				              0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK				             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK         0x0000001FU
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH				 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK        0x00FF0000U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH				8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK             0x03000000U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH				     2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK				              0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK				             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH               6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH          8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK     0x00FF0000U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK				              0x07030101U
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK				             0x07030101U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOSET               0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET				  0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK            0x00030000U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH				    2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK              0x07000000U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH				      3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK				              0x01010101U
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK				             0x01010101U
+#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET          0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH				1U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR				0U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET				0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET        0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET              0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK				              0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK				             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH				11U
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK          0x3FFF0000U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH				 14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK				              0x00003FFFU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH            14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0
+
+#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_WIDTH        14U
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK				              0x00001F1FU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK				             0x00001F1FU
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK  0x0000001FU
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH          5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH     5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0
+
+#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 5U
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK				              0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK				             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK             0x00000007U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH				     3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT				     8U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH				    16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK            0x07000000U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH				    3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK				              0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK				             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH				   16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH				   2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_MASK   0x7F000000U
+#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK				              0xFF01037FU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK				             0xFF01037FU
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK    0x0000007FU
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH            7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK         0x00000300U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH				 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH				       1U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR				       0U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET				       0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH				  8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK				              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK              0x000007FFU
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH				     11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK               0x07FF0000U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH				      11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK				              0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK				             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK             0x000000FFU
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH				     8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT				     8U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH				    10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET               0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK				              0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK				             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK    0x0000003FU
+#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH            6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK				0x00000F00U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT				        8U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH				        4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK				 0x001F0000U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT				        16U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH				         5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT				      24U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK				              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT				       8U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT				      24U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK				              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT				       8U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH				       5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH				      5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK				              0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK				             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH				     5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH				    5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH				  6U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK				              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK				              0x000703FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH				  10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK        0x00070000U
+#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH				3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH				       8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH				  8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH				  8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH				      8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK				              0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK				             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH				4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH				 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK           0x00FF0000U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH				   8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT				24U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH				 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH				16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH				 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK				             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH				1U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR				0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET				0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH				      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH				     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH				  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK				             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK				            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK				   0x00000003U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH				           2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK				  0x00000100U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT				          8U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET				          0U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH				5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK          0x1F000000U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH				  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK				             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH				    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK        0x0007FF00U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT				24U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH				 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK				             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK         0x000000FFU
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH				 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK               0x000F0000U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH				       4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK            0xFF000000U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH				    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK				             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_MASK       0x00003F00U
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH				    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_MASK       0x1F000000U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH				 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK				             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH				   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT               8U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH				1U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR				0U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET				0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH				    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH				   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK				             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK             0x000003FFU
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH				    10U
+#define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOSET               0U
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_MASK    0x3F000000U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_WIDTH            6U
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK				             0x00030703U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH				3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK				             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK				             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT      24U
+#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK				             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH				     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH              6U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH				     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH				   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK				             0x0000000FU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH				    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK				             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK				             0x0003FF03U
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_128_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_129_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_130_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_131_READ_MASK				             0x03FF070FU
+#define LPDDR4__DENALI_PHY_131_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH				3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_132_READ_MASK				             0x000103FFU
+#define LPDDR4__DENALI_PHY_132_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_132
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_133_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_133_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_134_READ_MASK				             0x010F07FFU
+#define LPDDR4__DENALI_PHY_134_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH				   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK				  0x01000000U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT				         24U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET				          0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_135_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_135_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_136_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_137_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_137
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_137
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_137
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT           24U
+#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_138_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_138
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_138
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_139_READ_MASK				             0x0003033FU
+#define LPDDR4__DENALI_PHY_139_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK				    0x00000300U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT				            8U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH				            2U
+#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139
+#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0
+
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK				   0x00030000U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH				           2U
+#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139
+#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
new file mode 100644
index 0000000000..124f58f7e8
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2373 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK				             0x000F07FFU
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK				             0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK				             0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH				     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH				    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH				   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK				             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT         8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT      24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK				             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT     8U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT     16U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK				             0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH				      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH				      9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK				             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK        0x0000007FU
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH				7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK         0x0001FF00U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH				 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK				             0x007F3F01U
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK            0x007F0000U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH				    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET				  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK				             0x070101FFU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK				     0x00010000U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT				            16U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH				             1U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR				             0U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET				             0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK				 0x07000000U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT				        24U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH				         3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK				             0x000301FFU
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK         0x00030000U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH				 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH				32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK				             0x00000301U
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET				    0U
+#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273
+#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT				     8U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH				     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK				             0x070F0107U
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH				 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK				             0xFF030001U
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET				    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET				 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK				0x00030000U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH				        2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK           0xFF000000U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH				   8U
+#define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK				             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH				           8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK				             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK				             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH				     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH         8U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH				   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH				  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK				             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK               0x00000007U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH				       3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT   8U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK      0x0F000000U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK				             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH        1U
+#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR        0U
+#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH				9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK				0x0000FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH				       16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET				    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK				             0x00FF0001U
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH				   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH				      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH				  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK				             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK				             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK				             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH				      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH				 17U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH				  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1
+
+#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH				 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK				             0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH				 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH               32U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH				32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK				             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK				            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK				  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH				         31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK				             0x0000003FU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK				            0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK				  0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH				          6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH				     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK				             0x010001FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH				1U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR				0U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET				0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET				   0U
+#define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322
+#define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK        0x000000FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH				8U
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_SHIFT       8U
+#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WIDTH       1U
+#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOCLR       0U
+#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOSET       0U
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK				 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH				        18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH				       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK				             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK				            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK				0x000007FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH				       11U
+#define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK           0x01FF0000U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH				   9U
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK				             0x017F7F01U
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET				    0U
+#define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK          0x00007F00U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH				  7U
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK        0x007F0000U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH				7U
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK				             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK         0x00000FFFU
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH				12U
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK            0x07FF0000U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH				   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK				             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK        0x0000001FU
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH				5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK            0x03000000U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH				    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK				             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT         8U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK				             0x07030101U
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET				 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH				   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK             0x07000000U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH				     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK				             0x01010101U
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH         1U
+#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR         0U
+#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH       1U
+#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR       0U
+#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK				             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH               11U
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK         0x3FFF0000U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH				14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK    0x00003FFFU
+#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH           14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1
+
+#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_WIDTH       14U
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK				             0x00001F1FU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH         5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_SHIFT    8U
+#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_WIDTH    5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1
+
+#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_WIDTH 5U
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK				             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH				    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH				   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH				   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK				             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH				  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH				  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_SHIFT         24U
+#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK				             0xFF01037FU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH				2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH				      1U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR				      0U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET				      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT				24U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH				 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH				    11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH				     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK				             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH				    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH				   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK				             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT				       8U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH				       4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK				0x001F0000U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH				        5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH				     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK				             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH				    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH				   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH				 6U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH				 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_MASK       0x00070000U
+#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH				      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT				16U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH				     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK				             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH				  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH				16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH				 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK				             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH				1U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR				0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET				0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH				      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH				     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH				  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK				             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK				            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK				   0x00000003U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH				           2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK				  0x00000100U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT				          8U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET				          0U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH				5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK          0x1F000000U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH				  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK				             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH				    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK        0x0007FF00U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT				24U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH				 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK				             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK         0x000000FFU
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH				 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT         8U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK               0x000F0000U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH				       4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK            0xFF000000U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH				    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK				             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_MASK       0x00003F00U
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH				    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_MASK       0x1F000000U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH				 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK				             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH				   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH				1U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR				0U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET				0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH				    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH				   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK				             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK             0x000003FFU
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH				    10U
+#define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOSET               0U
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_MASK    0x3F000000U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_WIDTH            6U
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK				             0x00030703U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH				3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK				             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK				             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT      24U
+#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK				             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH				     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH              6U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH				     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH				   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK				             0x0000000FU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH				    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK				             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK				             0x0003FF03U
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_384_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_385_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_386_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_387_READ_MASK				             0x03FF070FU
+#define LPDDR4__DENALI_PHY_387_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH				3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_388_READ_MASK				             0x000103FFU
+#define LPDDR4__DENALI_PHY_388_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_388
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_389_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_389_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_390_READ_MASK				             0x010F07FFU
+#define LPDDR4__DENALI_PHY_390_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH				   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK				  0x01000000U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT				         24U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET				          0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_391_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_391_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_392_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_393_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_393
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_393
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_393
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_394_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_394
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_394
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_395_READ_MASK				             0x0003033FU
+#define LPDDR4__DENALI_PHY_395_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK				    0x00000300U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT				            8U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH				            2U
+#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395
+#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1
+
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK				   0x00030000U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH				           2U
+#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395
+#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
new file mode 100644
index 0000000000..7c3756ca85
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
@@ -0,0 +1,2373 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK				             0x000F07FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK				             0x010303FFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT     0U
+#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK				             0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH				     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH				    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH				   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
+
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT     24U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH      1U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR      0U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK				             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT      24U
+#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK				             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT     8U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT     16U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK				             0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH				      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH				      9U
+#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK				             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK        0x0000007FU
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH				7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523
+#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK         0x0001FF00U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH				 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK				             0x007F3F01U
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH      1U
+#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR      0U
+#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2
+
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK            0x007F0000U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH				    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524
+#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT       0U
+#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_525
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2
+
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET				  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK				             0x070101FFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK				     0x00010000U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT				            16U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH				             1U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR				             0U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET				             0U
+#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2
+
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK				 0x07000000U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT				        24U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH				         3U
+#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526
+#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK				             0x000301FFU
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_527
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK         0x00030000U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH				 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH				32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528
+#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK				             0x00000301U
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET				    0U
+#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529
+#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT				     8U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH				     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529
+#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530
+#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531
+#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532
+#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533
+#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534
+#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535
+#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536
+#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537
+#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK				             0x070F0107U
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH				 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK				             0xFF030001U
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET				    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET				 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK				0x00030000U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH				        2U
+#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2
+
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK           0xFF000000U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH				   8U
+#define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540
+#define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK				             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH				           8U
+#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541
+#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK				             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK				             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH				     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2
+
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT        24U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH         8U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH				   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT      16U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
+
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH				  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK				             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK               0x00000007U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH				       3U
+#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2
+
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT   8U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK      0x0F000000U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK				             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_546
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH        1U
+#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR        0U
+#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH				9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548
+#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549
+#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550
+#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551
+#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK				0x0000FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH				       16U
+#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552
+#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2
+
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET				    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552
+#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_553
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2
+
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2
+
+#define LPDDR4__DENALI_PHY_555_READ_MASK				             0x00FF0001U
+#define LPDDR4__DENALI_PHY_555_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2
+
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH				   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH				      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555
+#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2
+
+#define LPDDR4__DENALI_PHY_556_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH				  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556
+#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_557_READ_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_558_READ_MASK				             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_559_READ_MASK				             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560_READ_MASK				             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH				      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560
+#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_561_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_562_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH				 17U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_563_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_564_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH				  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2
+
+#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_565_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_565_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2
+
+#define LPDDR4__DENALI_PHY_566_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH				 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_567_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_567
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_568_READ_MASK				             0x00000003U
+#define LPDDR4__DENALI_PHY_568_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
+
+#define LPDDR4__DENALI_PHY_569_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH				 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_570_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH               32U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2
+
+#define LPDDR4__DENALI_PHY_571_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_571
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_572_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH				32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2
+
+#define LPDDR4__DENALI_PHY_573_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2
+
+#define LPDDR4__DENALI_PHY_574_READ_MASK				             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574_WRITE_MASK				            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK				  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH				         31U
+#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574
+#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_575_READ_MASK				             0x0000003FU
+#define LPDDR4__DENALI_PHY_575_WRITE_MASK				            0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK				  0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH				          6U
+#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575
+#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_576_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH				     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576
+#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_577_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_578_READ_MASK				             0x010001FFU
+#define LPDDR4__DENALI_PHY_578_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_578
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH				1U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR				0U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET				0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2
+
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET				   0U
+#define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578
+#define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_579_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK        0x000000FFU
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH				8U
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_SHIFT       8U
+#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WIDTH       1U
+#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOCLR       0U
+#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOSET       0U
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2
+
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
+#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
+
+#define LPDDR4__DENALI_PHY_580_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
+
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
+#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
+
+#define LPDDR4__DENALI_PHY_581_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
+
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
+#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
+
+#define LPDDR4__DENALI_PHY_582_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
+
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
+#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
+
+#define LPDDR4__DENALI_PHY_583_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_583_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
+#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
+
+#define LPDDR4__DENALI_PHY_584_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK				 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH				        18U
+#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
+#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
+
+#define LPDDR4__DENALI_PHY_585_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
+
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH				       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
+#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
+
+#define LPDDR4__DENALI_PHY_586_READ_MASK				             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586_WRITE_MASK				            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK				0x000007FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH				       11U
+#define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2
+
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK           0x01FF0000U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH				   9U
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_587_READ_MASK				             0x017F7F01U
+#define LPDDR4__DENALI_PHY_587_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET				    0U
+#define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK          0x00007F00U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH				  7U
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK        0x007F0000U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT               16U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH				7U
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2
+
+#define LPDDR4__DENALI_PHY_588_READ_MASK				             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK         0x00000FFFU
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH				12U
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2
+
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK            0x07FF0000U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH				   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2
+
+#define LPDDR4__DENALI_PHY_589_READ_MASK				             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK        0x0000001FU
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH				5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2
+
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK            0x03000000U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH				    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589
+#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2
+
+#define LPDDR4__DENALI_PHY_590_READ_MASK				             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2
+
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2
+
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2
+
+#define LPDDR4__DENALI_PHY_591_READ_MASK				             0x07030101U
+#define LPDDR4__DENALI_PHY_591_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET				 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH				   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2
+
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK             0x07000000U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH				     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591
+#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_592_READ_MASK				             0x01010101U
+#define LPDDR4__DENALI_PHY_592_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH         1U
+#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR         0U
+#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT      16U
+#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH       1U
+#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR       0U
+#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_593_READ_MASK				             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH               11U
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2
+
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK         0x3FFF0000U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH				14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2
+
+#define LPDDR4__DENALI_PHY_594_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_594_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK    0x00003FFFU
+#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH           14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__REG DENALI_PHY_594
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2
+
+#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_WIDTH       14U
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2
+
+#define LPDDR4__DENALI_PHY_595_READ_MASK				             0x00001F1FU
+#define LPDDR4__DENALI_PHY_595_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH         5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2
+
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_SHIFT    8U
+#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_WIDTH    5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__REG DENALI_PHY_595
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2
+
+#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_WIDTH 5U
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2
+
+#define LPDDR4__DENALI_PHY_596_READ_MASK				             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH				    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH				   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH				   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_597_READ_MASK				             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH				  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH				  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2
+
+#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2
+
+#define LPDDR4__DENALI_PHY_598_READ_MASK				             0xFF01037FU
+#define LPDDR4__DENALI_PHY_598_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH				2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH				      1U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR				      0U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET				      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2
+
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT				24U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH				 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2
+
+#define LPDDR4__DENALI_PHY_599_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH				    11U
+#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2
+
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH				     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599
+#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2
+
+#define LPDDR4__DENALI_PHY_600_READ_MASK				             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH				    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2
+
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH				   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_601_READ_MASK				             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT				       8U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH				       4U
+#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2
+
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK				0x001F0000U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH				        5U
+#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2
+
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601
+#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2
+
+#define LPDDR4__DENALI_PHY_602_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2
+
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2
+
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2
+
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602
+#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2
+
+#define LPDDR4__DENALI_PHY_603_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2
+
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2
+
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2
+
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH				     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603
+#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_604_READ_MASK				             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH				    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH				   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2
+
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH				 6U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_605_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_606_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_607_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_608_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_609_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_609_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH				 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_MASK       0x00070000U
+#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_610_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH				      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT				16U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH				     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610
+#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_611_READ_MASK				             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH				  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2
+
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT               24U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2
+
+#define LPDDR4__DENALI_PHY_612_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH				16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2
+
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH				 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2
+
+#define LPDDR4__DENALI_PHY_613_READ_MASK				             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH				1U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR				0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET				0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH				      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH				     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH				  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2
+
+#define LPDDR4__DENALI_PHY_614_READ_MASK				             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614_WRITE_MASK				            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK				   0x00000003U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH				           2U
+#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK				  0x00000100U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT				          8U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET				          0U
+#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT               16U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH				5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2
+
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK          0x1F000000U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH				  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2
+
+#define LPDDR4__DENALI_PHY_615_READ_MASK				             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH				    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK        0x0007FF00U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT				24U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH				 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615
+#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_616_READ_MASK				             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK         0x000000FFU
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH				 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK               0x000F0000U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH				       4U
+#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK            0xFF000000U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH				    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616
+#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_617_READ_MASK				             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2
+
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_MASK       0x00003F00U
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH				    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_MASK       0x1F000000U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT              24U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_618_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618
+#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2
+
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH				 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2
+
+#define LPDDR4__DENALI_PHY_619_READ_MASK				             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH				   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT               8U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT               16U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH				1U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR				0U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET				0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2
+
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH				    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619
+#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_620_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_620_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH				   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2
+
+#define LPDDR4__DENALI_PHY_621_READ_MASK				             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK             0x000003FFU
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH				    10U
+#define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WIDTH               1U
+#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOCLR               0U
+#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOSET               0U
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_MASK    0x3F000000U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_WIDTH            6U
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_622_READ_MASK				             0x00030703U
+#define LPDDR4__DENALI_PHY_622_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH				3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2
+
+#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_SHIFT             16U
+#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_623_READ_MASK				             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_623
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_624_READ_MASK				             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT      24U
+#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
+
+#define LPDDR4__DENALI_PHY_625_READ_MASK				             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH				     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2
+
+#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT              8U
+#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH              6U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH				     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625
+#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2
+
+#define LPDDR4__DENALI_PHY_626_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH				   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_627_READ_MASK				             0x0000000FU
+#define LPDDR4__DENALI_PHY_627_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH				    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_628_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_630_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632_READ_MASK				             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_633_READ_MASK				             0x0003FF03U
+#define LPDDR4__DENALI_PHY_633_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT        8U
+#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_640_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_641_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_642_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_643_READ_MASK				             0x03FF070FU
+#define LPDDR4__DENALI_PHY_643_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH				3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2
+
+#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT      16U
+#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_644_READ_MASK				             0x000103FFU
+#define LPDDR4__DENALI_PHY_644_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_644
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2
+
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH            1U
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR            0U
+#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2
+
+#define LPDDR4__DENALI_PHY_645_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_645_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2
+
+#define LPDDR4__DENALI_PHY_646_READ_MASK				             0x010F07FFU
+#define LPDDR4__DENALI_PHY_646_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH				   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2
+
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK				  0x01000000U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT				         24U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET				          0U
+#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646
+#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2
+
+#define LPDDR4__DENALI_PHY_647_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_647_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT      0U
+#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
+
+#define LPDDR4__DENALI_PHY_648_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_649_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_649
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT            8U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_649
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_649
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_650_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_650
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_650
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2
+
+#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT       16U
+#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
+
+#define LPDDR4__DENALI_PHY_651_READ_MASK				             0x0003033FU
+#define LPDDR4__DENALI_PHY_651_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
+
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK				    0x00000300U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT				            8U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH				            2U
+#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651
+#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2
+
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK				   0x00030000U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH				           2U
+#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651
+#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2
+
+#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
new file mode 100644
index 0000000000..bfde51d358
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
@@ -0,0 +1,2373 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK				             0x000F07FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK				             0x010303FFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT     0U
+#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK				             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH				    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK				             0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH				     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH				    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH				   2U
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
+
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT     24U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH      1U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR      0U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET      0U
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
+#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK				             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET             0U
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT         8U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT      24U
+#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK				             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT     8U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT     16U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK				             0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH				      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK              0x0001FF00U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH				      9U
+#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK				             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK        0x0000007FU
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH				7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779
+#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3
+
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK         0x0001FF00U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH				 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3
+
+#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT          24U
+#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH           1U
+#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR           0U
+#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK				             0x007F3F01U
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH      1U
+#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR      0U
+#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3
+
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK            0x007F0000U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH				    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780
+#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT       0U
+#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_781
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3
+
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH				  1U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR				  0U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET				  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK				             0x070101FFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK				     0x00010000U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT				            16U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH				             1U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR				             0U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET				             0U
+#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3
+
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK				 0x07000000U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT				        24U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH				         3U
+#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782
+#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK				             0x000301FFU
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK    0x000001FFU
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_783
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK         0x00030000U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH				 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH				32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784
+#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK				             0x00000301U
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET				    0U
+#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785
+#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK             0x00000300U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT				     8U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH				     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785
+#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786
+#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH				      32U
+#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787
+#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788
+#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789
+#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790
+#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791
+#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792
+#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH				     32U
+#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793
+#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK				             0x070F0107U
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH           1U
+#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR           0U
+#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH				 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK				             0xFF030001U
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET				    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3
+
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET				 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK				0x00030000U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH				        2U
+#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3
+
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK           0xFF000000U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH				   8U
+#define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796
+#define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK				             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH				           8U
+#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797
+#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK				             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK				             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH				     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3
+
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT        24U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH         8U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH				   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT      16U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
+
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH				  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK				             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK               0x00000007U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT				       0U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH				       3U
+#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3
+
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT   8U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK      0x0F000000U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT             24U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK				             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_802
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3
+
+#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH        1U
+#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR        0U
+#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH				9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804
+#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805
+#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806
+#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH				       32U
+#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807
+#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK				0x0000FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH				       16U
+#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808
+#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3
+
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET				    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808
+#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_809
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT          0U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3
+
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT         16U
+#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3
+
+#define LPDDR4__DENALI_PHY_811_READ_MASK				             0x00FF0001U
+#define LPDDR4__DENALI_PHY_811_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT          0U
+#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH          1U
+#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR          0U
+#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3
+
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH				   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3
+
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH				      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811
+#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3
+
+#define LPDDR4__DENALI_PHY_812_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH				  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812
+#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3
+
+#define LPDDR4__DENALI_PHY_813_READ_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3
+
+#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3
+
+#define LPDDR4__DENALI_PHY_814_READ_MASK				             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3
+
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_815_READ_MASK				             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT       24U
+#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816_READ_MASK				             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT          8U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH				      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816
+#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3
+
+#define LPDDR4__DENALI_PHY_817_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_818_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH				 17U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_819_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
+
+#define LPDDR4__DENALI_PHY_820_READ_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH				  16U
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820
+#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3
+
+#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_821_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_821_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3
+
+#define LPDDR4__DENALI_PHY_822_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH				 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_823_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_823
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_824_READ_MASK				             0x00000003U
+#define LPDDR4__DENALI_PHY_824_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT    0U
+#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
+
+#define LPDDR4__DENALI_PHY_825_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH				 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_826_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH               32U
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826
+#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3
+
+#define LPDDR4__DENALI_PHY_827_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_827
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_828_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH				32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3
+
+#define LPDDR4__DENALI_PHY_829_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3
+
+#define LPDDR4__DENALI_PHY_830_READ_MASK				             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830_WRITE_MASK				            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK				  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH				         31U
+#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830
+#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3
+
+#define LPDDR4__DENALI_PHY_831_READ_MASK				             0x0000003FU
+#define LPDDR4__DENALI_PHY_831_WRITE_MASK				            0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK				  0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT				          0U
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH				          6U
+#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831
+#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3
+
+#define LPDDR4__DENALI_PHY_832_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH				     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832
+#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3
+
+#define LPDDR4__DENALI_PHY_833_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3
+
+#define LPDDR4__DENALI_PHY_834_READ_MASK				             0x010001FFU
+#define LPDDR4__DENALI_PHY_834_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_834
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH				1U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR				0U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET				0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3
+
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET				   0U
+#define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834
+#define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3
+
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834
+#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3
+
+#define LPDDR4__DENALI_PHY_835_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK        0x000000FFU
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH				8U
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_SHIFT       8U
+#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WIDTH       1U
+#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOCLR       0U
+#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOSET       0U
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3
+
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
+#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
+
+#define LPDDR4__DENALI_PHY_836_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
+
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
+#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
+
+#define LPDDR4__DENALI_PHY_837_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
+
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
+#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
+
+#define LPDDR4__DENALI_PHY_838_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
+
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK				0x01FF0000U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
+#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
+
+#define LPDDR4__DENALI_PHY_839_READ_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_839_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
+#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
+
+#define LPDDR4__DENALI_PHY_840_READ_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK				 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT				         0U
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH				        18U
+#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
+#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
+
+#define LPDDR4__DENALI_PHY_841_READ_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK				0x000001FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH				        9U
+#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
+
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH				       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
+#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
+
+#define LPDDR4__DENALI_PHY_842_READ_MASK				             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842_WRITE_MASK				            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK				0x000007FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT				        0U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH				       11U
+#define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3
+
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK           0x01FF0000U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH				   9U
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842
+#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3
+
+#define LPDDR4__DENALI_PHY_843_READ_MASK				             0x017F7F01U
+#define LPDDR4__DENALI_PHY_843_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH				    1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR				    0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET				    0U
+#define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK          0x00007F00U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT				  8U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH				  7U
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK        0x007F0000U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT               16U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH				7U
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH				   1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR				   0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET				   0U
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843
+#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3
+
+#define LPDDR4__DENALI_PHY_844_READ_MASK				             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK         0x00000FFFU
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH				12U
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3
+
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK            0x07FF0000U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH				   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3
+
+#define LPDDR4__DENALI_PHY_845_READ_MASK				             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK        0x0000001FU
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH				5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH           8U
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH               8U
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3
+
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK            0x03000000U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH				    2U
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845
+#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3
+
+#define LPDDR4__DENALI_PHY_846_READ_MASK				             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH              6U
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3
+
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT         8U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3
+
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT            24U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846
+#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3
+
+#define LPDDR4__DENALI_PHY_847_READ_MASK				             0x07030101U
+#define LPDDR4__DENALI_PHY_847_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH				 1U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR				 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET				 0U
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH				   2U
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3
+
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK             0x07000000U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH				     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847
+#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_848_READ_MASK				             0x01010101U
+#define LPDDR4__DENALI_PHY_848_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH         1U
+#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR         0U
+#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT      16U
+#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH       1U
+#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR       0U
+#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT            24U
+#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_849_READ_MASK				             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH               11U
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3
+
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK         0x3FFF0000U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH				14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3
+
+#define LPDDR4__DENALI_PHY_850_READ_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_850_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK    0x00003FFFU
+#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH           14U
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__REG DENALI_PHY_850
+#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3
+
+#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_WIDTH       14U
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850
+#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3
+
+#define LPDDR4__DENALI_PHY_851_READ_MASK				             0x00001F1FU
+#define LPDDR4__DENALI_PHY_851_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH         5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3
+
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_SHIFT    8U
+#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_WIDTH    5U
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__REG DENALI_PHY_851
+#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3
+
+#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_WIDTH 5U
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851
+#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3
+
+#define LPDDR4__DENALI_PHY_852_READ_MASK				             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH				    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH				   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT				  24U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH				   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_853_READ_MASK				             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH				  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH				  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3
+
+#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_SHIFT         24U
+#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3
+
+#define LPDDR4__DENALI_PHY_854_READ_MASK				             0xFF01037FU
+#define LPDDR4__DENALI_PHY_854_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH				2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH				      1U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR				      0U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET				      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3
+
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT				24U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH				 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3
+
+#define LPDDR4__DENALI_PHY_855_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH				    11U
+#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3
+
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH				     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855
+#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3
+
+#define LPDDR4__DENALI_PHY_856_READ_MASK				             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH				    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3
+
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT				    8U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH				   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3
+
+#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT             24U
+#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3
+
+#define LPDDR4__DENALI_PHY_857_READ_MASK				             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT				       8U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH				       4U
+#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3
+
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK				0x001F0000U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT				       16U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH				        5U
+#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3
+
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857
+#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3
+
+#define LPDDR4__DENALI_PHY_858_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3
+
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3
+
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3
+
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT				     24U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858
+#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3
+
+#define LPDDR4__DENALI_PHY_859_READ_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3
+
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3
+
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT				     16U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH				      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3
+
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH				     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859
+#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_860_READ_MASK				             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH				    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT				   8U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH				   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3
+
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH				 6U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3
+
+#define LPDDR4__DENALI_PHY_861_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_862_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_863_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_864_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_865_READ_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_865_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT				  0U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH				 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_MASK       0x00070000U
+#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH               3U
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865
+#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3
+
+#define LPDDR4__DENALI_PHY_866_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT				      0U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH				      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT				 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT				16U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH				 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT				    24U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH				     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866
+#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_867_READ_MASK				             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH				  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3
+
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT               24U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH				8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3
+
+#define LPDDR4__DENALI_PHY_868_READ_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH				16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3
+
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH				 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3
+
+#define LPDDR4__DENALI_PHY_869_READ_MASK				             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH				1U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR				0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET				0U
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT				      8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH				      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH				     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK          0x03000000U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH				  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3
+
+#define LPDDR4__DENALI_PHY_870_READ_MASK				             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870_WRITE_MASK				            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK				   0x00000003U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT				           0U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH				           2U
+#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK				  0x00000100U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT				          8U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET				          0U
+#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT               16U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH				5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3
+
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK          0x1F000000U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT				 24U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH				  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3
+
+#define LPDDR4__DENALI_PHY_871_READ_MASK				             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH				    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3
+
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK        0x0007FF00U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3
+
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT				24U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH				 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871
+#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3
+
+#define LPDDR4__DENALI_PHY_872_READ_MASK				             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK         0x000000FFU
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT				 0U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH				 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT         8U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK               0x000F0000U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT				      16U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH				       4U
+#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3
+
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK            0xFF000000U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH				    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872
+#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_873_READ_MASK				             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3
+
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_MASK       0x00003F00U
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT				   16U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH				    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_MASK       0x1F000000U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT              24U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3
+
+#define LPDDR4__DENALI_PHY_874_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH				  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874
+#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3
+
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT				 16U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH				 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3
+
+#define LPDDR4__DENALI_PHY_875_READ_MASK				             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT				   0U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH				   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT               8U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT               16U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH				1U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR				0U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET				0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3
+
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT				   24U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH				    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875
+#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3
+
+#define LPDDR4__DENALI_PHY_876_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_876_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH				   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3
+
+#define LPDDR4__DENALI_PHY_877_READ_MASK				             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK             0x000003FFU
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH				    10U
+#define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WIDTH               1U
+#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOCLR               0U
+#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOSET               0U
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3
+
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_MASK    0x3F000000U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_WIDTH            6U
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877
+#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3
+
+#define LPDDR4__DENALI_PHY_878_READ_MASK				             0x00030703U
+#define LPDDR4__DENALI_PHY_878_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT               0U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH				3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3
+
+#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_MASK      0x00030000U
+#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_SHIFT             16U
+#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_WIDTH              2U
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878
+#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3
+
+#define LPDDR4__DENALI_PHY_879_READ_MASK				             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_879
+#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH        11U
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879
+#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
+
+#define LPDDR4__DENALI_PHY_880_READ_MASK				             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH              1U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR              0U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET              0U
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH             1U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR             0U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET             0U
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH         8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT      24U
+#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH       8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880
+#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
+
+#define LPDDR4__DENALI_PHY_881_READ_MASK				             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK             0x0000007FU
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT				     0U
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH				     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3
+
+#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT              8U
+#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH              6U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3
+
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK             0x001F0000U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT				    16U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH				     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881
+#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3
+
+#define LPDDR4__DENALI_PHY_882_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH				   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3
+
+#define LPDDR4__DENALI_PHY_883_READ_MASK				             0x0000000FU
+#define LPDDR4__DENALI_PHY_883_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT				    0U
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH				    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3
+
+#define LPDDR4__DENALI_PHY_884_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_886_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887_READ_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT             0U
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888_READ_MASK				             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT            16U
+#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_889_READ_MASK				             0x0003FF03U
+#define LPDDR4__DENALI_PHY_889_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT        8U
+#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_896_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_897_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT        16U
+#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_898_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_899_READ_MASK				             0x03FF070FU
+#define LPDDR4__DENALI_PHY_899_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT              0U
+#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH				3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3
+
+#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT      16U
+#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_900_READ_MASK				             0x000103FFU
+#define LPDDR4__DENALI_PHY_900_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_900
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3
+
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH            1U
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR            0U
+#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3
+
+#define LPDDR4__DENALI_PHY_901_READ_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_901_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_SHIFT              16U
+#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3
+
+#define LPDDR4__DENALI_PHY_902_READ_MASK				             0x010F07FFU
+#define LPDDR4__DENALI_PHY_902_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT         0U
+#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT				  16U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH				   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3
+
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK				  0x01000000U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT				         24U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH				          1U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR				          0U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET				          0U
+#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902
+#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3
+
+#define LPDDR4__DENALI_PHY_903_READ_MASK				             0x000003FFU
+#define LPDDR4__DENALI_PHY_903_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT      0U
+#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
+
+#define LPDDR4__DENALI_PHY_904_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT            8U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904
+#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_905_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_905
+#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK    0x0000FF00U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT            8U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_905
+#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK    0x00FF0000U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT           16U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_905
+#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT           24U
+#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905
+#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_906_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT            0U
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH            8U
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_906
+#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK     0x0000FF00U
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT             8U
+#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH             8U
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_906
+#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3
+
+#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT       16U
+#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
+
+#define LPDDR4__DENALI_PHY_907_READ_MASK				             0x0003033FU
+#define LPDDR4__DENALI_PHY_907_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT        0U
+#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
+
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK				    0x00000300U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT				            8U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH				            2U
+#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907
+#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3
+
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK				   0x00030000U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT				          16U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH				           2U
+#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907
+#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3
+
+#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000000..274a976ef9
--- /dev/null
+++ b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,7793 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK				               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK				              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK				             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT								     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH								     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR								     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET								     0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK				        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT								8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH								4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK				     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH				            16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK				               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH				     32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK				               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH				     32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK				               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK				              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK				       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT				               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH				               5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK				       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH				               4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK				        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT				               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH								2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT				     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH				      8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK				               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH				  8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT				     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH				     8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT				16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH				 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK				               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH				   16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH				8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH				          8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK				               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH				   8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT				    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH				    8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT				 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH				  8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK				               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK				          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH								 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK				               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK				         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH								24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK				               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK				         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH								24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT								0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH				               24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK				         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH								24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH				               24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH				               24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH				               24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK				         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH								24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT								0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH				               24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT								0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH				               24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK				              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK				             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK				        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT								0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH				               24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK				 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT				        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET				         0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK				              0x01010101U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK				             0x01010101U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK				 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET				         0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK				  0x00000100U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET				          0U
+#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
+#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
+
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK				      0x00010000U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET				              0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK				        0x01000000U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH								1U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR								0U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET								0U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK				              0x03013F01U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK				             0x03013F01U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH				     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR				     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET				     0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK				    0x00003F00U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT				            8U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH				            6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT				     16U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH				      1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR				      0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET				      0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK				 0x03000000U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT				        24U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH				         2U
+#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
+#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK				              0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK				             0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK				 0x00000003U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH				         2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK				   0x00001F00U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH				           5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK				   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH				           5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK				   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH				           5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK				              0x00030303U
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK				             0x00030303U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH				      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT				      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH				      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT				     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH				      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK				       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT				               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH				              32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK				     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH				            32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK				              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK				             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK				     0x00000001U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET				             0U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK				     0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH				            24U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK				              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK				     0x000000FFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH				             8U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK				     0x0000FF00U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH				             8U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK				   0x00010000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH				           1U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR				           0U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET				           0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK				              0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK				             0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK				   0x00007FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH				          15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK				0x000F0000U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH				        4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK				         0xFF000000U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT								24U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH								 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK				         0x000000FFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH								 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK				         0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT								 8U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH								 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK           0x00FF0000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH				   8U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK           0xFF000000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT				  24U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH				   8U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH				          8U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK        0x0000FF00U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT				8U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH				8U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK               0xFFFF0000U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT				      16U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH				      16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK				              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK				             0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK				  0x00000001U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET				          0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT				     8U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT				    16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
+
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT				    16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT				    16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK				              0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK				             0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH				    16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
+
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK				    0x007F0000U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT				           16U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH				            7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK				         0x7F000000U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT								24U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH								 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK				              0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK				             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK				    0x0000007FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH				            7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK				         0x00007F00U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT								 8U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH								 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK				    0x007F0000U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT				           16U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH				            7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK				         0x7F000000U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT								24U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH								 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK				              0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK				             0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK				0x00000007U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH				        3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_36__TCCD_MASK				             0x00001F00U
+#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT								     8U
+#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH								     5U
+#define LPDDR4__TCCD__REG DENALI_CTL_36
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
+
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK				          0x00FF0000U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH								  8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_36
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK				              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK				             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK				           0x000001FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH								   9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_37
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
+
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK				      0x00FF0000U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH				              8U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK				          0x3F000000U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH								  6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_37
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK				              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK				             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK				           0x000000FFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH								   8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_38
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
+
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK				          0x0001FF00U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH								  9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_38
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK				          0xFF000000U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH								  8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_38
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK				              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK				             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK				           0x000001FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH								   9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_39
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
+
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK				      0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH				              8U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK				          0x3F000000U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH								  6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_39
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK				              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK				             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK				           0x000000FFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH								   8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_40
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
+
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK				          0x0001FF00U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH								  9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_40
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK				          0xFF000000U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH								  8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_40
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK				              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK				             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK				           0x000001FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH								   9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_41
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
+
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK				      0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH				              8U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK				          0x3F000000U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH								  6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_41
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK				              0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK				             0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK				           0x000000FFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH								   8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_42
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
+
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK				          0x0001FF00U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH								  9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_42
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK				           0x3F000000U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH								   6U
+#define LPDDR4__TCCDMW__REG DENALI_CTL_42
+#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK				          0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH								  8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_43
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH								  8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK				          0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH								  8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK				              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK				             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK				      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH				             17U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK				          0x1F000000U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH								  5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_44
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK				        0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT								0U
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH								8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH								  8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_45
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK				          0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH								  8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK				          0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH								  8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK				              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK				             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK				      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH				             17U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK				          0x1F000000U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH								  5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_46
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK				        0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH								8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH								  8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_47
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK				          0x00FF0000U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH								  8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK				          0xFF000000U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH								  8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK				              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK				             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK				      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH				             17U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK				          0x1F000000U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH								  5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_48
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK				              0x070707FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK				             0x070707FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK				        0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT								0U
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH								8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_49__TPPD_MASK				             0x00000700U
+#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT								     8U
+#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH								     3U
+#define LPDDR4__TPPD__REG DENALI_CTL_49
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK				     0x00070000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH				             3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK				     0x07000000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH				             3U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK				              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK				             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK				      0x00000001U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET				              0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH								  8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK				           0x00FF0000U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT								  16U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH								   8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_50
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK				          0xFF000000U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH								  8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK				              0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK				           0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH								   8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_51
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
+
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH								  8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK				           0x00FF0000U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT								  16U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH								   8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_51
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
+
+#define LPDDR4__DENALI_CTL_51__TMRR_MASK				             0x0F000000U
+#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT								    24U
+#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH								     4U
+#define LPDDR4__TMRR__REG DENALI_CTL_51
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK				              0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK				             0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK				          0x0000001FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH								  5U
+#define LPDDR4__TCACKEL__REG DENALI_CTL_52
+#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
+
+#define LPDDR4__DENALI_CTL_52__TCAENT_MASK				           0x0003FF00U
+#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT								   8U
+#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH								  10U
+#define LPDDR4__TCAENT__REG DENALI_CTL_52
+#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
+
+#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK				           0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH								   6U
+#define LPDDR4__TCAMRD__REG DENALI_CTL_52
+#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK				              0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK				           0x0000001FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH								   5U
+#define LPDDR4__TCAEXT__REG DENALI_CTL_53
+#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
+
+#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK				          0x00001F00U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH								  5U
+#define LPDDR4__TCACKEH__REG DENALI_CTL_53
+#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK				          0x001F0000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH								  5U
+#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK				          0x1F000000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH								  5U
+#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK				              0x0101011FU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK				             0x0101011FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK				          0x0000001FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH								  5U
+#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
+#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
+
+#define LPDDR4__DENALI_CTL_54__AP_MASK				               0x00000100U
+#define LPDDR4__DENALI_CTL_54__AP_SHIFT								       8U
+#define LPDDR4__DENALI_CTL_54__AP_WIDTH								       1U
+#define LPDDR4__DENALI_CTL_54__AP_WOCLR								       0U
+#define LPDDR4__DENALI_CTL_54__AP_WOSET								       0U
+#define LPDDR4__AP__REG DENALI_CTL_54
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
+
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK				     0x00010000U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET				             0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK				     0x01000000U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET				             0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK				              0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK				             0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK				          0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH								  8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK				          0x0000FF00U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH								  8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK				          0x00FF0000U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH								  8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK				           0x1F000000U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH								   5U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_55
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK				      0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH				              8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK				      0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH				              8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK				      0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH				              8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK				      0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT				             24U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH				              8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK				              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK				             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK				      0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH				              8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK				      0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH				              8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK				  0x00010000U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET				          0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK				     0x03000000U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH				             2U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK				              0x0101017FU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK				             0x0101017FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK				     0x0000007FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH				             7U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK				 0x00000100U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT				         8U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET				         0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK				     0x00010000U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET				             0U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK				     0x01000000U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET				             0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK				              0x07010100U
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK				             0x07010100U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK				         0x00000001U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH								 1U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR								 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET								 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_59
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
+
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK				      0x00000100U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET				              0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK				      0x00010000U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET				              0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK				     0x07000000U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH				             3U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK				              0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK				             0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x0000003FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          0U
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK				          0x0003FF00U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT								  8U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH								 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_60
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK				              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK				          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH								 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_61
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK				              0x000003FFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK				             0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK				          0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH								 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_62
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK				              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK				          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH								 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_63
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK				              0x000003FFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK				             0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK				          0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH								 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_64
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK				              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK				          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH								 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_65
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK				              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK				    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH				           20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK				              0x03FF0101U
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK				             0x03FF0101U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK				           0x00000001U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT								   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH								   1U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR								   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET								   0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_67
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
+
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK				0x00000100U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT				        8U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET				        0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK				       0x03FF0000U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH				              10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK				              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK				             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK				      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH				             16U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK				       0x03FF0000U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH				              10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK				              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK				             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK				      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH				             16U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK				       0x03FF0000U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH				              10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK				      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH				             16U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK				0xFFFF0000U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH				       16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK				              0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK				             0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK            0x0000000FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH				    4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK				  0x00000100U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET				          0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x001F0000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT              16U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x1F000000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             24U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK				         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH								16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK				         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT								16U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH								16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK				         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH								16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK				         0x00FF0000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT								16U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH								 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK				         0xFF000000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT								24U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH								 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK				              0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK				             0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK				         0x000000FFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH								 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK				        0x00001F00U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT								8U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH								5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH				               5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK				       0x1F000000U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT				              24U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH				               5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK				              0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK				             0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH				              5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK				        0x00000F00U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT								8U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH								4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK				0x00010000U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET				        0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK				        0x1F000000U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH								5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK				              0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK				             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK				       0x0000001FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT				               0U
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH				               5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK				       0x00001F00U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH				               5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK				      0x001F0000U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH				              5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK				        0x0F000000U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH								4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK				              0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK				             0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK				0x00000001U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET				        0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK				        0x00001F00U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT								8U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH								5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH				               5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK				       0x1F000000U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT				              24U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH				               5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK				              0x00010F1FU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK				             0x00010F1FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH				              5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK				        0x00000F00U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT								8U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH								4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK				0x00010000U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET				        0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK				          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH								 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK				         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT								16U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH								16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK				          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH								 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK				         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT								16U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH								16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK				          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH								 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK				         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT								16U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH								16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK				              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK				             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH				              5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK				      0x00001F00U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH				              5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH				               5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK				           0xFF000000U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH								   8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_82
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK				              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK				             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK				        0x00000007U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT								0U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH								3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK				       0x00001F00U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH				               5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH				               5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK				       0x1F000000U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT				              24U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH				               5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK				              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK				             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH				              5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK				      0x00001F00U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH				              5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH				               5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK				           0xFF000000U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH								   8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_84
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK				              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK				             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK				        0x00000007U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH								3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK				       0x00001F00U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH				               5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH				               5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK				       0x1F000000U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT				              24U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH				               5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK				              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK				             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH				              5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK				      0x00001F00U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH				              5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH				               5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK				           0xFF000000U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT								  24U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH								   8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_86
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK				              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK				             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK				        0x00000007U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT								0U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH								3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK				       0x00001F00U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH				               5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK				       0x001F0000U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT				              16U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH				               5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK				       0x1F000000U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT				              24U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH				               5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK				              0x07010101U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK				             0x07010101U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH				      1U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR				      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET				      0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK				    0x00000100U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT				            8U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH				            1U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR				            0U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET				            0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT				   16U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET				    0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK				        0x07000000U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH								3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK				              0x01010300U
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK				             0x01010300U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK				    0x0000001FU
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH				            5U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK				       0x00000300U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT				               8U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH				               2U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK				        0x00010000U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT				               16U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH								1U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR								0U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET								0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK				     0x01000000U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET				             0U
+#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK				              0x00010101U
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK				             0x00010101U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK				     0x00000001U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET				             0U
+#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK				     0x00000100U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET				             0U
+#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK				0x00010000U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET				        0U
+#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT				16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK				              0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK				             0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK				    0x00070000U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT				           16U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH				            3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK				    0x07000000U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT				           24U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH				            3U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK				              0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK				             0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK				    0x00000007U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH				            3U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK				    0x0000FF00U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT				            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH				            8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK				    0x00FF0000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT				           16U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH				            8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK				    0xFF000000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT				           24U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH				            8U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT            0U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT           16U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH				  16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT     16U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT      0U
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH     16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT           16U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT            0U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH				  16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT     16U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH     16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT            0U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT           16U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK				             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH				    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK				             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH				   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH				    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK				             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK				             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH				   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH				    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK				             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK				             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK				            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH				   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK				 0x01000000U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT				        24U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET				         0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK				             0x00010103U
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK				            0x00010103U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH				    2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH				 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT				 16U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH				 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK				     0x00010000U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET				             0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK				     0x07000000U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH				             3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK				             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK				            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK				 0x000000FFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH				         8U
+#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
+#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
+
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK				 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT				         8U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH				        17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK				             0x01030107U
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK				            0x01030107U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK				0x00000007U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH				        3U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK				  0x00000100U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET				          0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK				      0x00030000U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH				              2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK               0x01000000U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT				      24U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH				       1U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR				       0U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET				       0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK				             0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK				            0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH				 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK				        0x0000FF00U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT								8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH								8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK				        0x00FF0000U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT				               16U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH								8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK				        0xFF000000U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH								8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK				            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK				        0x000000FFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT								0U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH								8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK				        0x0000FF00U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT								8U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH								8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK				        0x00FF0000U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT				               16U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH								8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK				          0x7F000000U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT								 24U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH								  7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_132
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH				 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK          0x00000F00U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT				  8U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH				  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH				   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT       24U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK				0x0000000FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH				        4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x00000F00U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT				8U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH				4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT				16U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH				 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT     24U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH				     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK         0x00000F00U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT				 8U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH				 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT				 16U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH				  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT				  24U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH				   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT        0U
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK				0x00000F00U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT				        8U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH				        4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x000F0000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH				4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x0F000000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT				24U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH				 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT      0U
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK             0x00000F00U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT				     8U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH				     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT				16U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH				 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK          0x0F000000U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT				 24U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH				  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK           0x0000000FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH				   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT        8U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK				0x000F0000U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH				        4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x0F000000U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT               24U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH				4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK				             0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK				            0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH				 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT      8U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT				    16U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH				     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK				   0x3F000000U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH				           6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK				             0x070FFF01U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK				            0x070FFF01U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK				 0x00000001U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET				         0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK              0x000FFF00U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT				      8U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH				     12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK				    0x07000000U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT				           24U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH				            3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK				             0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK				            0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK				    0x0000007FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH				            7U
+#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
+
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK				    0x00007F00U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT				            8U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH				            7U
+#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK				0x000F0000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH				        4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK				 0x0F000000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT				        24U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH				         4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK				             0x000FFF07U
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK				            0x000FFF07U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH				     3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK				 0x000FFF00U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT				         8U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH				        12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK				             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK				            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH				  12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT				   16U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH				    8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT				16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT				 0U
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT				0U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK				             0x01010101U
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT				       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH				       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR				       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET				       0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK				0x00000100U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT				        8U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH				        1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR				        0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET				        0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT				      16U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH				       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR				       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET				       0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK				   0x01000000U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH				           1U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR				           0U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET				           0U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK				             0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK				            0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK				    0x00000001U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT				            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH				            1U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR				            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET				            0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK				     0x00000100U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH				             1U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR				             0U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET				             0U
+#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK            0x003F0000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT				   16U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH				    6U
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK             0x3F000000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT				    24U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH				     6U
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK				             0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK				            0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK            0x000000FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH				    8U
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
+
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK				   0x00000300U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH				           2U
+#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
+
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH				           8U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK				      0x01000000U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT				             24U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET				              0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK				             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH				     10U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH				  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK				             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH				     10U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH				  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK				             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH				     10U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT				  16U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH				  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK				             0x00000103U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK				            0x00000103U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK				0x00000003U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH				        2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT				    8U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET				    0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH				 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK				             0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK				            0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT				  0U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH				  4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT				  8U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH				 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK				   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH				          27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK				             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK				            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK				      0x000000FFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH				              8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK				    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT				            8U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH				           17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH				  32U
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK				             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK				            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT				   0U
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH				   8U
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
+
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT				      8U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH				     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH				     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT				   16U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET				    0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK				             0x03FF0003U
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK				            0x03FF0003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT				      0U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH				      2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK				 0x03FF0000U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT				        16U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH				        10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK				0x000003FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH				       10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK				          0x03FF0000U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH								 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_165
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK				             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK				            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH				              5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK				      0x00001F00U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH				              5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK				   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH				          16U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK				 0x000003FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH				        10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK				0x03FF0000U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT				       16U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH				       10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK				             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK				            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK				          0x000003FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT								  0U
+#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH								 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_168
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK				      0x001F0000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH				              5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK				      0x1F000000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT				             24U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH				              5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK				             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK				            0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK				   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH				          16U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK				 0x03FF0000U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT				        16U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH				        10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK				0x000003FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH				       10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK				          0x03FF0000U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT								 16U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH								 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_170
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK				             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK				            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK				      0x0000001FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT				              0U
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH				              5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK				      0x00001F00U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH				              5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK				   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH				          16U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT				0U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT				0U
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT				0U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK				 0x00FF0000U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT				        16U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH				         8U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK				      0x0000FF00U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH				              8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK				  0x00FF0000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK				  0x00FF0000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK				     0x000000FFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH				             8U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK				  0x00FF0000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK				     0x000000FFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH				             8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK				     0x0000FF00U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH				             8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK				     0x00FF0000U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH				             8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK				 0x000000FFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH				         8U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK				   0xFF000000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT				          24U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK				   0x000000FFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT				           0U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK				   0x0000FF00U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK				   0x00FF0000U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK				      0xFF000000U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT				             24U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH				              8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK				  0x00FF0000U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK				     0x00FF0000U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH				             8U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK				  0x000000FFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK				     0x00FF0000U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT				            16U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH				             8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK				     0xFF000000U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT				            24U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH				             8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK				     0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT				             0U
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH				             8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK				  0x0000FF00U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK				  0x00FF0000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK				  0xFF000000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK				             0x010101FFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK				            0x010101FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK				       0x000000FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT				               0U
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH				               8U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_190
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT				    8U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET				    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT				   16U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET				    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK            0x01000000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT				   24U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET				    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK				             0x01010103U
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK				            0x01010103U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK				  0x00000003U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH				          2U
+#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
+#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK				   0x00000100U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT				           8U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH				           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR				           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET				           0U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK				   0x00010000U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH				           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR				           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET				           0U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT				     24U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH				      1U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR				      0U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET				      0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK				             0x01010101U
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH				    1U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR				    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET				    0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK				      0x00000100U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT				              8U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH				              1U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR				              0U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET				              0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK				  0x00010000U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT				         16U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET				          0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK				  0x01000000U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT				         24U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET				          0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK				             0x03030101U
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK				            0x03030101U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK				  0x00000001U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET				          0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK				  0x00000100U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET				          0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK				        0x00030000U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT				               16U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH								2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK				        0x03000000U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT				               24U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH								2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK				             0x013F0300U
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK				            0x013F0300U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK				         0x00000001U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT								 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH								 1U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR								 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET								 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_194
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
+
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK				     0x00000300U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT				             8U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH				             2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK				      0x003F0000U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH				              6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK				 0x01000000U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT				        24U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET				         0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK				             0x00000001U
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK				            0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK				 0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT				         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH				         1U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR				         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET				         0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH				   32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK				             0x00000007U
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK				            0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK            0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT				    0U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH				    3U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH				       32U
+#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
+#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK				0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT				        0U
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH				       32U
+#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
+#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK				             0x00000007U
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK				            0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK				  0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH				          3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH				    32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH				    32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH				    32U
+#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
+#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH				    32U
+#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
+#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK				             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK				            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT				     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH				     1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR				     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET				     0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK				  0x00000100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT				          8U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH				          1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR				          0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET				          0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK				   0x0FFF0000U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT				          16U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH				          12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK				             0x07030FFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK				            0x07030FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK				  0x00000FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT				          0U
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH				         12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK				      0x00030000U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT				             16U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH				              2U
+#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206