[U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code

[Simon Goldschmidt]

Marek Vasut <marex at denx.de> schrieb am Mi., 9. Okt. 2019, 23:01:

> On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
> [...]
> >>>>>>> Based on my understand through this register
> >>>>>>> fpga_mgr_fpgamgrdata
> >>>>>>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> >>>>>>> of
> >>>>>>> FIFO
> >>>>>>> buffer is mapping to above range addresses.
> >>>>>> 0xFFCFE7FF-0xFFCFE400 = 0x400 = 1024 Bytes , not 256 . Why ?
> >>>>> Finally, i have connected all scattered dot information from few
> >>>>> internal docs. The register fpga_mgr_fpgamgrdata is actually a
> >>>>> space in
> >>>>> memory, acting like a buffer for the FPGA data. Regardless of the
> >>>>> programming mode, data input from this buffer is translated into a
> >>>>> 32-
> >>>>> bit wide data path used by the configuration logic.
> >>>> Does that mean that a write anywhere in 0xFFCFE400..0xFFCFE7FF ends
> >>>> up
> >>>> in the same register / FIFO ? Does that mean that whole address range
> >>>> ignores the bottom 0x3ff MSbits ? Does it matter to which address in
> >>>> that range the CPU writes the data or not ?
> >>>
> >>> Sorry, that's all information i have. Anyway, i have already engaged
> >>> the HW engineer in the loop, and i will update you once i have more
> >>> details.
> >>
> >> Thanks, let's wait and see ...
> >
> > Have you dropped this? It's assigned to me in patchwork (I'm going
> > through the list of old items assigned to me...).
>
> I don't know, sorry. Apparently there isn't enough information to decide
> whether this patch is correct or not.
>

Right. However, since it seems to work as is, I don't think we have a real
problem.

Regards,
Simon

>