[U-Boot] [PATCH v4 2/4] arm: socfpga: Convert reset manager from struct to defines

Ley Foon Tan ley.foon.tan at intel.com
Thu Oct 10 07:37:32 UTC 2019


Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

---
v4:
- Update commit message about get base address from DT node.

v3:
- Remove "No functional change" in commit description.

v2:
- Get base address from DT
- Revert to use writel(), readl(), setbits_le32() and clrbits_le32().
- Add prefix to defines.
---
 arch/arm/mach-socfpga/include/mach/misc.h     |  1 +
 .../mach-socfpga/include/mach/reset_manager.h |  2 +
 .../include/mach/reset_manager_arria10.h      | 43 ++++-------------
 .../include/mach/reset_manager_gen5.h         | 22 ++++-----
 .../include/mach/reset_manager_s10.h          | 33 ++-----------
 arch/arm/mach-socfpga/misc.c                  | 32 +++++++++++++
 arch/arm/mach-socfpga/misc_gen5.c             |  7 ++-
 arch/arm/mach-socfpga/reset_manager_arria10.c | 47 ++++++++++---------
 arch/arm/mach-socfpga/reset_manager_gen5.c    | 28 +++++------
 arch/arm/mach-socfpga/reset_manager_s10.c     | 34 +++++++-------
 arch/arm/mach-socfpga/spl_a10.c               |  7 ++-
 arch/arm/mach-socfpga/spl_gen5.c              | 12 ++---
 arch/arm/mach-socfpga/spl_s10.c               | 12 +++--
 drivers/sysreset/sysreset_socfpga.c           |  6 +--
 14 files changed, 137 insertions(+), 149 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 27d0b6a370..a29b049742 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
 
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
+void socfpga_get_manager_addr(void);
 
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..a5b6931350 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
 #ifndef _RESET_MANAGER_H_
 #define _RESET_MANAGER_H_
 
+extern phys_addr_t socfpga_rstmgr_base;
+
 void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..41169aa677 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_deassert_osc1wd0(void);
 int socfpga_bridges_reset(void);
 
-struct socfpga_reset_manager {
-	u32	stat;
-	u32	ramstat;
-	u32	miscstat;
-	u32	ctrl;
-	u32	hdsken;
-	u32	hdskreq;
-	u32	hdskack;
-	u32	counts;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	sysmodrst;
-	u32	coldmodrst;
-	u32	nrstmodrst;
-	u32	dbgmodrst;
-	u32	mpuwarmmask;
-	u32	per0warmmask;
-	u32	per1warmmask;
-	u32	brgwarmmask;
-	u32	syswarmmask;
-	u32	nrstwarmmask;
-	u32	l3warmmask;
-	u32	tststa;
-	u32	tstscratch;
-	u32	hdsktimeout;
-	u32	hmcintr;
-	u32	hmcintren;
-	u32	hmcintrens;
-	u32	hmcintrenr;
-	u32	hmcgpout;
-	u32	hmcgpin;
-};
+#define RSTMGR_A10_STATUS		0
+#define RSTMGR_A10_CTRL		0xc
+#define RSTMGR_A10_MPUMODRST	0x20
+#define RSTMGR_A10_PER0MODRST	0x24
+#define RSTMGR_A10_PER1MODRST	0x28
+#define RSTMGR_A10_BRGMODRST	0x2c
+#define RSTMGR_A10_SYSMODRST	0x30
+
+#define RSTMGR_CTRL		RSTMGR_A10_CTRL
 
 /*
  * SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..e51ebfd08f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
 void socfpga_bridges_reset(int enable);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	ctrl;
-	u32	counts;
-	u32	padding1;
-	u32	mpu_mod_reset;
-	u32	per_mod_reset;
-	u32	per2_mod_reset;
-	u32	brg_mod_reset;
-	u32	misc_mod_reset;
-	u32	padding2[12];
-	u32	tstscratch;
-};
+#define RSTMGR_GEN5_STATUS	0
+#define RSTMGR_GEN5_CTRL	4
+#define RSTMGR_GEN5_MPUMODRST	0x10
+#define RSTMGR_GEN5_PERMODRST	0x14
+#define RSTMGR_GEN5_PER2MODRST	0x18
+#define RSTMGR_GEN5_BRGMODRST	0x1c
+#define RSTMGR_GEN5_MISCMODRST	0x20
+
+#define RSTMGR_CTRL		RSTMGR_GEN5_CTRL
 
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..b602129656 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	mpu_rst_stat;
-	u32	misc_stat;
-	u32	padding1;
-	u32	hdsk_en;
-	u32	hdsk_req;
-	u32	hdsk_ack;
-	u32	hdsk_stall;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	padding2;
-	u32     cold_mod_reset;
-	u32	padding3;
-	u32     dbg_mod_reset;
-	u32     tap_mod_reset;
-	u32	padding4;
-	u32	padding5;
-	u32     brg_warm_mask;
-	u32	padding6[3];
-	u32     tst_stat;
-	u32	padding7;
-	u32     hdsk_timeout;
-	u32     mpul2flushtimeout;
-	u32     dbghdsktimeout;
-};
+#define RSTMGR_S10_STATUS		0
+#define RSTMGR_S10_MPUMODRST	0x20
+#define RSTMGR_S10_PER0MODRST	0x24
+#define RSTMGR_S10_PER1MODRST	0x28
+#define RSTMGR_S10_BRGMODRST	0x2c
 
 #define RSTMGR_MPUMODRST_CORE0		0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 49dadd4c3d..901c432f82 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -22,6 +22,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+phys_addr_t socfpga_rstmgr_base __section(".data");
+
 #ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -145,6 +147,8 @@ void socfpga_fpga_add(void *fpga_desc)
 
 int arch_cpu_init(void)
 {
+	socfpga_get_manager_addr();
+
 #ifdef CONFIG_HW_WATCHDOG
 	/*
 	 * In case the watchdog is enabled, make sure to (re-)configure it
@@ -202,3 +206,31 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
 );
 
 #endif
+
+static phys_addr_t socfpga_get_base_addr(const char *compat)
+{
+	const void *blob = gd->fdt_blob;
+	struct fdt_resource r;
+	int node;
+	int ret;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return 0;
+
+	if (!fdtdec_get_is_enabled(blob, node))
+		return 0;
+
+	ret = fdt_get_resource(blob, node, "reg", 0, &r);
+	if (ret)
+		return 0;
+
+	return (phys_addr_t)r.start;
+}
+
+void socfpga_get_manager_addr(void)
+{
+	socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
+	if (!socfpga_rstmgr_base)
+		hang();
+}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..b39a66562d 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -206,8 +206,6 @@ int arch_early_init_r(void)
 }
 
 #ifndef CONFIG_SPL_BUILD
-static struct socfpga_reset_manager *reset_manager_base =
-	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 static struct socfpga_sdr_ctrl *sdr_ctrl =
 	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
@@ -226,12 +224,13 @@ void do_bridge_reset(int enable, unsigned int mask)
 
 		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
-		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[0],
+		       socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
 		writel(iswgrp_handoff[1], &nic301_regs->remap);
 	} else {
 		writel(0, &sysmgr_regs->fpgaintfgrp_module);
 		writel(0, &sdr_ctrl->fpgaport_rst);
-		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
 		writel(1, &nic301_regs->remap);
 	}
 }
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 471a3045af..4553653992 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,8 +15,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
 		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
 void socfpga_watchdog_disable(void)
 {
 	/* assert reset for watchdog */
-	setbits_le32(&reset_manager_base->per1modrst,
+	setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
 /* Release NOC ddr scheduler from reset */
 void socfpga_reset_deassert_noc_ddr_scheduler(void)
 {
-	clrbits_le32(&reset_manager_base->brgmodrst,
+	clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
 		     ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
 }
 
@@ -103,7 +101,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
 	setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
 
 	/* Release bridges from reset state per handoff value */
-	clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+	clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
 
 	/* Poll until all idleack to 0, timeout at 1000ms */
 	return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
@@ -113,7 +111,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 void socfpga_reset_deassert_osc1wd0(void)
 {
-	clrbits_le32(&reset_manager_base->per1modrst,
+	clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
 		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 }
 
@@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
  */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const u32 *reg;
+	unsigned long reg;
 	u32 rstmgr_bank = RSTMGR_BANK(reset);
 
 	switch (rstmgr_bank) {
 	case 0:
-		reg = &reset_manager_base->mpumodrst;
+		reg = RSTMGR_A10_MPUMODRST;
 		break;
 	case 1:
-		reg = &reset_manager_base->per0modrst;
+		reg = RSTMGR_A10_PER0MODRST;
 		break;
 	case 2:
-		reg = &reset_manager_base->per1modrst;
+		reg = RSTMGR_A10_PER1MODRST;
 		break;
 	case 3:
-		reg = &reset_manager_base->brgmodrst;
+		reg = RSTMGR_A10_BRGMODRST;
 		break;
 	case 4:
-		reg = &reset_manager_base->sysmodrst;
+		reg = RSTMGR_A10_SYSMODRST;
 		break;
 
 	default:
@@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
 	}
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -174,11 +174,12 @@ void socfpga_per_reset_all(void)
 		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 
 	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
-	writel(~l4wd0, &reset_manager_base->per1modrst);
-	setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+	writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST);
+	setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST,
+		     ~mask_ecc_ocp);
 
 	/* Finally disable the ECC_OCP */
-	setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+	setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST, mask_ecc_ocp);
 }
 
 int socfpga_bridges_reset(void)
@@ -224,13 +225,13 @@ int socfpga_bridges_reset(void)
 		return ret;
 
 	/* Put all bridges (except NOR DDR scheduler) into reset state */
-	setbits_le32(&reset_manager_base->brgmodrst,
+	setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
 		     (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
-		     ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+		      ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
 
 	/* Disable NOC timeout */
 	writel(0, &sysmgr_regs->noc_timeout);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..ad31214711 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,32 +10,30 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const u32 *reg;
+	unsigned long reg;
 	u32 rstmgr_bank = RSTMGR_BANK(reset);
 
 	switch (rstmgr_bank) {
 	case 0:
-		reg = &reset_manager_base->mpu_mod_reset;
+		reg = RSTMGR_GEN5_MPUMODRST;
 		break;
 	case 1:
-		reg = &reset_manager_base->per_mod_reset;
+		reg = RSTMGR_GEN5_PERMODRST;
 		break;
 	case 2:
-		reg = &reset_manager_base->per2_mod_reset;
+		reg = RSTMGR_GEN5_PER2MODRST;
 		break;
 	case 3:
-		reg = &reset_manager_base->brg_mod_reset;
+		reg = RSTMGR_GEN5_BRGMODRST;
 		break;
 	case 4:
-		reg = &reset_manager_base->misc_mod_reset;
+		reg = RSTMGR_GEN5_MISCMODRST;
 		break;
 
 	default:
@@ -43,9 +41,11 @@ void socfpga_per_reset(u32 reset, int set)
 	}
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -57,8 +57,8 @@ void socfpga_per_reset_all(void)
 {
 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
-	writel(~l4wd0, &reset_manager_base->per_mod_reset);
-	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+	writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_GEN5_PERMODRST);
+	writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_GEN5_PER2MODRST);
 }
 
 #define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
@@ -95,7 +95,7 @@ void socfpga_bridges_reset(int enable)
 
 	if (enable) {
 		/* brdmodrst */
-		writel(0x7, &reset_manager_base->brg_mod_reset);
+		writel(0x7, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
 		writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
 	} else {
 		socfpga_bridges_set_handoff_regs(false, false, false);
@@ -109,7 +109,7 @@ void socfpga_bridges_reset(int enable)
 		}
 
 		/* brdmodrst */
-		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
 
 		/* Remap the bridges into memory map */
 		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..b196d58d3d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_reset_manager *reset_manager_base =
-		(void *)SOCFPGA_RSTMGR_ADDRESS;
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
 {
-	const void *reg;
+	unsigned long reg;
 
 	if (RSTMGR_BANK(reset) == 0)
-		reg = &reset_manager_base->mpumodrst;
+		reg = RSTMGR_S10_MPUMODRST;
 	else if (RSTMGR_BANK(reset) == 1)
-		reg = &reset_manager_base->per0modrst;
+		reg = RSTMGR_S10_PER0MODRST;
 	else if (RSTMGR_BANK(reset) == 2)
-		reg = &reset_manager_base->per1modrst;
+		reg = RSTMGR_S10_PER1MODRST;
 	else if (RSTMGR_BANK(reset) == 3)
-		reg = &reset_manager_base->brgmodrst;
+		reg = RSTMGR_S10_BRGMODRST;
 	else	/* Invalid reset register, do nothing */
 		return;
 
 	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		setbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+		clrbits_le32(socfpga_rstmgr_base + reg,
+			     1 << RSTMGR_RESET(reset));
 }
 
 /*
@@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
 
 	/* disable all except OCP and l4wd0. OCP disable later */
 	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
-	       &reset_manager_base->per0modrst);
-	writel(~l4wd0, &reset_manager_base->per0modrst);
-	writel(0xffffffff, &reset_manager_base->per1modrst);
+		      socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+	writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+	writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
 }
 
 void socfpga_bridges_reset(int enable)
@@ -62,7 +62,7 @@ void socfpga_bridges_reset(int enable)
 		setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
 
 		/* Release all bridges from reset state */
-		clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+		clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
 
 		/* Poll until all idleack to 0 */
 		while (readl(&system_manager_base->noc_idleack))
@@ -85,9 +85,9 @@ void socfpga_bridges_reset(int enable)
 			;
 
 		/* Reset all bridges (except NOR DDR scheduler & F2S) */
-		setbits_le32(&reset_manager_base->brgmodrst,
+		setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
 			     ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
-			     RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+			       RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 
 		/* Disable NOC timeout */
 		writel(0, &system_manager_base->noc_timeout);
@@ -99,6 +99,6 @@ void socfpga_bridges_reset(int enable)
  */
 int cpu_has_been_warmreset(void)
 {
-	return readl(&reset_manager_base->status) &
-		RSTMGR_L4WD_MPU_WARMRESET_MASK;
+	return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
+			RSTMGR_L4WD_MPU_WARMRESET_MASK;
 }
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b820cb0673..a0d80fd47e 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -106,6 +106,11 @@ void spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+	if (spl_early_init())
+		hang();
+
+	socfpga_get_manager_addr();
+
 	dcache_disable();
 
 	socfpga_init_security_policies();
@@ -116,8 +121,6 @@ void board_init_f(ulong dummy)
 	socfpga_per_reset_all();
 	socfpga_watchdog_disable();
 
-	spl_early_init();
-
 	/* Configure the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad..9ee053da3a 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -67,6 +67,12 @@ void board_init_f(ulong dummy)
 	int ret;
 	struct udevice *dev;
 
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_manager_addr();
+
 	/*
 	 * First C code to run. Clear fake OCRAM ECC first as SBE
 	 * and DBE might triggered during power on
@@ -128,12 +134,6 @@ void board_init_f(ulong dummy)
 	debug_uart_init();
 #endif
 
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
 	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 	if (ret)
 		debug("Reset init failed: %d\n", ret);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index ec65e1ce64..9a97a84e1e 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -14,6 +14,7 @@
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/firewall_s10.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <watchdog.h>
@@ -120,6 +121,12 @@ void board_init_f(ulong dummy)
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
 	int ret;
 
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_manager_addr();
+
 #ifdef CONFIG_HW_WATCHDOG
 	/* Ensure watchdog is paused when debugging is happening */
 	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
@@ -145,11 +152,6 @@ void board_init_f(ulong dummy)
 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 	debug_uart_init();
 #endif
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
 
 	preloader_console_init();
 	cm_print_clock_quick_summary();
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index d6c26a5b23..3390b7bdc2 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -12,7 +12,7 @@
 #include <asm/arch/reset_manager.h>
 
 struct socfpga_sysreset_data {
-	struct socfpga_reset_manager *rstmgr_base;
+	void __iomem *rstmgr_base;
 };
 
 static int socfpga_sysreset_request(struct udevice *dev,
@@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
 	switch (type) {
 	case SYSRESET_WARM:
 		writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	case SYSRESET_COLD:
 		writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	default:
 		return -EPROTONOSUPPORT;
-- 
2.19.0



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