[U-Boot] [PATCH 089/126] x86: Set up the MTRR for SDRAM

[Simon Glass]

Hi Bin,

On Thu, 10 Oct 2019 at 03:19, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <sjg at chromium.org> wrote:
> >
> > Set up MTRRs for the FST SDRAM regions to improve performance.
> >
> > Signed-off-by: Simon Glass <sjg at chromium.org>
> > ---
> >
> >  arch/x86/lib/fsp/fsp_dram.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
> > index 9161af65b98..4a87516f422 100644
> > --- a/arch/x86/lib/fsp/fsp_dram.c
> > +++ b/arch/x86/lib/fsp/fsp_dram.c
> > @@ -8,6 +8,7 @@
> >  #include <asm/fsp/fsp_support.h>
> >  #include <asm/e820.h>
> >  #include <asm/mrccache.h>
> > +#include <asm/mtrr.h>
> >  #include <asm/post.h>
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> > @@ -70,6 +71,8 @@ int dram_init_banksize(void)
> >         gd->bd->bi_dram[0].start = 0;
> >         gd->bd->bi_dram[0].size = low_end;
> >
> > +       mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
>
> I suspect we don't need explicit MTRR configuration. I see on the FSP
> 1.0 boards, MTRR is already programmed by FSP.
>
> But I am fine adding this. So if we are adding this MTRR, please also
> move MTRR programming from previous patch ([088/126] x86: Set the DRAM
> banks to reflect real location) to this patch.

The FSP does not seem to do this. However I wonder if I need to check
the version of my FSP.

Regards,
Simon