[U-Boot] [PATCH] pci: layerscape: remove multiple definitions of SVR
Z.q. Hou
zhiqiang.hou at nxp.com
Tue Oct 15 03:28:51 UTC 2019
Hi Pankaj,
> -----Original Message-----
> From: Pankaj Bansal
> Sent: 2019年10月14日 16:56
> To: Priyanka Jain <priyanka.jain at nxp.com>; Xiaowei Bao
> <xiaowei.bao at nxp.com>; Tom Rini <trini at konsulko.com>; Z.q. Hou
> <zhiqiang.hou at nxp.com>
> Cc: u-boot at lists.denx.de; Pankaj Bansal <pankaj.bansal at nxp.com>
> Subject: [PATCH] pci: layerscape: remove multiple definitions of SVR
>
> SVR values for various nxp SOCs are defined in asm/arch/soc.h we can use
> these values in any peripheral driver.
> we need not to redefine these values in peripheral driver, as this becomes
> difficult to manage (add or change new values)
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal at nxp.com>
> ---
> drivers/pci/pcie_layerscape.c | 11 ++++++-----
> drivers/pci/pcie_layerscape.h | 9 +--------
> drivers/pci/pcie_layerscape_fixup.c | 9 +++++----
> 3 files changed, 12 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index db1375a1ce..d8a7b7c865 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2017 NXP
> + * Copyright 2017, 2019 NXP
> * Copyright 2014-2015 Freescale Semiconductor, Inc.
> * Layerscape PCIe driver
> */
> @@ -15,6 +15,7 @@
> #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
> defined(CONFIG_ARM)
> #include <asm/arch/clock.h>
> +#include <asm/arch/soc.h>
> #endif
> #include "pcie_layerscape.h"
>
> @@ -56,7 +57,7 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
> uint svr;
>
> svr = get_svr();
> - if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) ==
> SVR_LS102XA) {
> + if ((SVR_DEV(svr) & SVR_LS102XA_MASK) == SVR_LS102XA) {
> state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
> state = (state >> LS1021_LTSSM_STATE_SHIFT) &
> LTSSM_STATE_MASK;
> } else {
> @@ -149,7 +150,7 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
> uint svr;
>
> svr = get_svr();
> - if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) ==
> SVR_LS102XA) {
> + if ((SVR_DEV(svr) & SVR_LS102XA_MASK) == SVR_LS102XA) {
> offset = LS1021_PCIE_SPACE_OFFSET +
> LS1021_PCIE_SPACE_SIZE * pcie->idx;
> }
> @@ -172,7 +173,7 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
> idx = PCIE_ATU_REGION_INDEX1 + 1;
>
> /* Fix the pcie memory map for LS2088A series SoCs */
> - svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
> + svr = SVR_SOC_VER(svr);
> if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> svr == SVR_LS2048A || svr == SVR_LS2044A ||
> svr == SVR_LS2081A || svr == SVR_LS2041A) { @@ -502,7 +503,7
> @@ static int ls_pcie_probe(struct udevice *dev)
> * for LS2088A series SoCs
> */
> svr = get_svr();
> - svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
> + svr = SVR_SOC_VER(svr);
> if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> svr == SVR_LS2048A || svr == SVR_LS2044A ||
> svr == SVR_LS2081A || svr == SVR_LS2041A) { diff --git
> a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index
> ddfbba6538..9a19993568 100644
> --- a/drivers/pci/pcie_layerscape.h
> +++ b/drivers/pci/pcie_layerscape.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Copyright 2017 NXP
> + * Copyright 2017, 2019 NXP
> * Copyright 2014-2015 Freescale Semiconductor, Inc.
> * Layerscape PCIe driver
> */
> @@ -111,14 +111,7 @@
> #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
>
> #define SVR_LS102XA 0
> -#define SVR_VAR_PER_SHIFT 8
> #define SVR_LS102XA_MASK 0x700
> -#define SVR_LS2088A 0x870900
> -#define SVR_LS2084A 0x870910
> -#define SVR_LS2048A 0x870920
> -#define SVR_LS2044A 0x870930
> -#define SVR_LS2081A 0x870918
> -#define SVR_LS2041A 0x870914
Keep in mind that LS1021A (armv7) also uses this driver and it will result in build error when removed them.
Thanks,
Zhiqiang
>
> /* LS1021a PCIE space */
> #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
> diff --git a/drivers/pci/pcie_layerscape_fixup.c
> b/drivers/pci/pcie_layerscape_fixup.c
> index 089e031724..9a09852981 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2017 NXP
> + * Copyright 2017, 2019 NXP
> * Copyright 2014-2015 Freescale Semiconductor, Inc.
> * Layerscape PCIe driver
> */
> @@ -16,6 +16,7 @@
> #ifdef CONFIG_ARM
> #include <asm/arch/clock.h>
> #endif
> +#include <asm/arch/soc.h>
> #include "pcie_layerscape.h"
>
> #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) @@ -83,7
> +84,7 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie
> *pcie,
> pcie->dbi_res.start);
> if (nodeoffset < 0) {
> #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts
> node */
> - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
> + svr = SVR_SOC_VER(get_svr());
> if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> svr == SVR_LS2048A || svr == SVR_LS2044A ||
> svr == SVR_LS2081A || svr == SVR_LS2041A) @@ -137,7
> +138,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct
> ls_pcie *pcie,
> pcie->dbi_res.start);
> if (nodeoffset < 0) {
> #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts
> node */
> - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
> + svr = SVR_SOC_VER(get_svr());
> if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> svr == SVR_LS2048A || svr == SVR_LS2044A ||
> svr == SVR_LS2081A || svr == SVR_LS2041A) @@ -228,7
> +229,7 @@ static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
> pcie->dbi_res.start);
> if (off < 0) {
> #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts
> node */
> - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
> + svr = SVR_SOC_VER(get_svr());
> if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> svr == SVR_LS2048A || svr == SVR_LS2044A ||
> svr == SVR_LS2081A || svr == SVR_LS2041A)
> --
> 2.17.1
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