[U-Boot] [RFC PATCH v2 10/18] ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata'
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Tue Oct 15 20:10:23 UTC 2019
In preparation to move handoff data from 'qts' files to devicetree, fetch
SDRAM config in 'of_to_platdata' DM callback. That way, this callback
can be changed to fetch the data from devicetree.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
---
Changes in v2: None
drivers/ddr/altera/sdram_gen5.c | 45 +++++++++++++++++++++++++--------
drivers/ddr/altera/sequencer.c | 35 +++++++++++++++----------
drivers/ddr/altera/sequencer.h | 9 ++++++-
3 files changed, 64 insertions(+), 25 deletions(-)
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8c8ea19eb9..91d9f6c0fc 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -25,6 +25,15 @@ struct altera_gen5_sdram_priv {
struct altera_gen5_sdram_platdata {
struct socfpga_sdr *sdr;
+ /* Handoff config follows */
+ const struct socfpga_sdram_config *cfg;
+ const struct socfpga_sdram_rw_mgr_config *rwcfg;
+ const struct socfpga_sdram_io_config *iocfg;
+ const struct socfpga_sdram_misc_config *misccf;
+ const u32 *inst_rom_init;
+ unsigned int inst_rom_init_len;
+ const u32 *ac_rom_init;
+ unsigned int ac_rom_init_len;
};
struct sdram_prot_rule {
@@ -43,7 +52,9 @@ struct sdram_prot_rule {
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
+static unsigned long sdram_calculate_size(
+ struct socfpga_sdr_ctrl *sdr_ctrl,
+ const struct socfpga_sdram_config *cfg);
/**
* get_errata_rows() - Up the number of DRAM rows to cover entire address space
@@ -446,10 +457,10 @@ static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
*
* Initialize the SDRAM MMR.
*/
-int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
- unsigned int sdr_phy_reg)
+static int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
+ unsigned int sdr_phy_reg,
+ const struct socfpga_sdram_config *cfg)
{
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
const unsigned int rows =
(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
@@ -481,7 +492,7 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
sdram_set_protection_config(sdr_ctrl, 0,
- sdram_calculate_size(sdr_ctrl) - 1);
+ sdram_calculate_size(sdr_ctrl, cfg) - 1);
sdram_dump_protection_config(sdr_ctrl);
@@ -494,11 +505,12 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
* Calculate SDRAM device size based on SDRAM controller parameters.
* Size is specified in bytes.
*/
-static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
+static unsigned long sdram_calculate_size(
+ struct socfpga_sdr_ctrl *sdr_ctrl,
+ const struct socfpga_sdram_config *cfg)
{
unsigned long temp;
unsigned long row, bank, col, cs, width;
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
const unsigned int csbits =
((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
@@ -565,6 +577,16 @@ static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
if (!plat->sdr)
return -ENODEV;
+ /* Get handoff config */
+ plat->cfg = socfpga_get_sdram_config();
+ plat->rwcfg = socfpga_get_sdram_rwmgr_config();
+ plat->iocfg = socfpga_get_sdram_io_config();
+ plat->misccf = socfpga_get_sdram_misc_config();
+
+ socfpga_get_seq_inst_init(&plat->inst_rom_init,
+ &plat->inst_rom_init_len);
+ socfpga_get_seq_ac_init(&plat->ac_rom_init, &plat->ac_rom_init_len);
+
return 0;
}
@@ -584,19 +606,22 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
}
reset_deassert_bulk(&resets);
- if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
+ if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff, plat->cfg) != 0) {
puts("SDRAM init failed.\n");
goto failed;
}
debug("SDRAM: Calibrating PHY\n");
/* SDRAM calibration */
- if (sdram_calibration_full(plat->sdr) == 0) {
+ if (sdram_calibration_full(plat->sdr, plat->rwcfg, plat->iocfg,
+ plat->misccf, plat->inst_rom_init,
+ plat->inst_rom_init_len, plat->ac_rom_init,
+ plat->ac_rom_init_len) == 0) {
puts("SDRAM calibration failed.\n");
goto failed;
}
- sdram_size = sdram_calculate_size(sdr_ctrl);
+ sdram_size = sdram_calculate_size(sdr_ctrl, plat->cfg);
debug("SDRAM: %ld MiB\n", sdram_size >> 20);
/* Sanity check ensure correct SDRAM size specified */
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6c632227c2..1e03cf3cf6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3655,21 +3655,20 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
*
* Initialize ROM data.
*/
-static void hc_initialize_rom_data(void)
+static void hc_initialize_rom_data(const u32 *inst_rom_init,
+ unsigned int inst_rom_init_len,
+ const u32 *ac_rom_init,
+ unsigned int ac_rom_init_len)
{
- unsigned int nelem = 0;
- const u32 *rom_init;
u32 i, addr;
- socfpga_get_seq_inst_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
- for (i = 0; i < nelem; i++)
- writel(rom_init[i], addr + (i << 2));
+ for (i = 0; i < inst_rom_init_len; i++)
+ writel(inst_rom_init[i], addr + (i << 2));
- socfpga_get_seq_ac_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
- for (i = 0; i < nelem; i++)
- writel(rom_init[i], addr + (i << 2));
+ for (i = 0; i < ac_rom_init_len; i++)
+ writel(ac_rom_init[i], addr + (i << 2));
}
/**
@@ -3788,7 +3787,14 @@ static void initialize_tracking(struct socfpga_sdrseq *seq)
&sdr_reg_file->trk_rfsh);
}
-int sdram_calibration_full(struct socfpga_sdr *sdr)
+int sdram_calibration_full(struct socfpga_sdr *sdr,
+ const struct socfpga_sdram_rw_mgr_config *rwcfg,
+ const struct socfpga_sdram_io_config *iocfg,
+ const struct socfpga_sdram_misc_config *misccfg,
+ const u32 *inst_rom_init,
+ unsigned int inst_rom_init_len,
+ const u32 *ac_rom_init,
+ unsigned int ac_rom_init_len)
{
u32 pass;
struct socfpga_sdrseq seq;
@@ -3802,9 +3808,9 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
memset(&seq, 0, sizeof(seq));
- seq.rwcfg = socfpga_get_sdram_rwmgr_config();
- seq.iocfg = socfpga_get_sdram_io_config();
- seq.misccfg = socfpga_get_sdram_misc_config();
+ seq.rwcfg = rwcfg;
+ seq.iocfg = iocfg;
+ seq.misccfg = misccfg;
/* Set the calibration enabled by default */
seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
@@ -3856,7 +3862,8 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve);
- hc_initialize_rom_data();
+ hc_initialize_rom_data(inst_rom_init, inst_rom_init_len,
+ ac_rom_init, ac_rom_init_len);
/* update info for sims */
reg_file_set_stage(CAL_STAGE_NIL);
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 4a03c3fdf9..84057d4b4f 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -278,6 +278,13 @@ struct socfpga_sdrseq {
struct param_type param;
};
-int sdram_calibration_full(struct socfpga_sdr *sdr);
+int sdram_calibration_full(struct socfpga_sdr *sdr,
+ const struct socfpga_sdram_rw_mgr_config *rwcfg,
+ const struct socfpga_sdram_io_config *iocfg,
+ const struct socfpga_sdram_misc_config *misccfg,
+ const u32 *inst_rom_init,
+ unsigned int inst_rom_init_len,
+ const u32 *ac_rom_init,
+ unsigned int ac_rom_init_len);
#endif /* _SEQUENCER_H_ */
--
2.20.1
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