[U-Boot] [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices

[Laurentiu Tudor]

On 18.10.2019 09:20, Priyanka Jain wrote:
> 
> 
>> -----Original Message-----
>> From: u-boot-bounces at linux.nxdi.nxp.com <u-boot-
>> bounces at linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>> Sent: Thursday, October 17, 2019 2:52 PM
>> To: u-boot at lists.denx.de; Prabhakar X <prabhakar.kushwaha at nxp.com>
>> Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform
>> devices
>>
>> From: Laurentiu Tudor <laurentiu.tudor at nxp.com>
>>
>> Add ICID setup for the platform devices contained on this chip: usb, sata,
>> sdhc, sec.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor at nxp.com>
>> ---
>> arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
>> .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++
>> arch/arm/cpu/armv8/fsl-layerscape/soc.c       |  2 +-
>> .../asm/arch-fsl-layerscape/immap_lsch3.h     |  4 +-
>> .../asm/arch-fsl-layerscape/stream_id_lsch3.h |  2 +
>> board/freescale/lx2160a/lx2160a.c             |  2 +
>> include/fsl_sec.h                             |  3 +-
>> 7 files changed, 58 insertions(+), 4 deletions(-)  create mode 100644
>> arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> index f00ef817b1..e398aecd12 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> @@ -24,6 +24,7 @@ endif
>>
>> ifneq ($(CONFIG_ARCH_LX2160A),)
>> obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
>> +obj-y += icid.o lx2160_ids.o
>> endif
>>
>> ifneq ($(CONFIG_ARCH_LS2080A),)
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> new file mode 100644
>> index 0000000000..3a0ed1fa55
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
>> @@ -0,0 +1,48 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2019 NXP
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch-fsl-layerscape/immap_lsch3.h>
>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
>> +
>> +struct icid_id_table icid_tbl[] = {
>> +	SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
>> +	SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
>> +	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +	SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
>> +	SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
>> +	SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
>> +	SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef
>> +CONFIG_FSL_CAAM
>> +	SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
>> +	SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
>> +	SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
>> +	SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
>> +	SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +	SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +	SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +	SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
>> +	SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif };
>> +
>> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> index 924f5f3fe8..4dea8361fc 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)  #endif
>>
>> #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
>> -	defined(CONFIG_ARCH_LS2080A)
>> +	defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
>> 	set_icids();
>> #endif
>> }
>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>> index 0e4bf331fd..f86835a33d 100644
>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>> @@ -447,7 +447,9 @@ struct ccsr_gur {
>> 	u8	res_538[0x550 - 0x538];	/* add more registers when needed */
>> 	u32	sata1_amqr;
>> 	u32	sata2_amqr;
>> -	u8	res_558[0x570-0x558];	/* add more registers when needed */
>> +	u32	sata3_amqr;
>> +	u32	sata4_amqr;
>> +	u8	res_558[0x570 - 0x560];	/* add more registers when needed */
> This will change the byte position for below variables.
> Please confirm that you have cross-checked and tested this update for all lsch3 SoC

I'm adding 8 bytes but adjusting the res_558 (which btw, I should rename 
it to res_560) by subtracting the previously added 8 bytes, so things 
should align properly as before.

---
Best Regards, Laurentiu