[U-Boot] [PATCH v3 026/108] x86: timer: Reduce timer code size in TPL on Intel CPUs

[Simon Glass]

Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 drivers/timer/Kconfig     | 9 +++++++++
 drivers/timer/tsc_timer.c | 7 +++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 0c922f54603..392bb5cc640 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -187,6 +187,15 @@ config X86_TSC_ZERO_BASE
 
 	  Enable this to always us an initial TSC value of 0.
 
+config TPL_X86_TSC_TIMER_NATIVE
+	bool "x86 TSC timer uses native calibration"
+	depends on TPL && X86_TSC_TIMER
+	help
+	  Selects native timer calibration for TPL and don't include the other
+	  methods in the code. This helps to reduce code size in TPL and works
+	  on fairly modern Intel chips. Code-size reductions is about 700
+	  bytes.
+
 config MTK_TIMER
 	bool "MediaTek timer support"
 	depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index ac7ba7fb00d..a4f208eb2fb 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -49,8 +49,7 @@ static unsigned long native_calibrate_tsc(void)
 		return 0;
 
 	crystal_freq = tsc_info.ecx / 1000;
-
-	if (!crystal_freq) {
+	if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
 		switch (gd->arch.x86_model) {
 		case INTEL_FAM6_SKYLAKE_MOBILE:
 		case INTEL_FAM6_SKYLAKE_DESKTOP:
@@ -406,6 +405,10 @@ static void tsc_timer_ensure_setup(bool early)
 		if (fast_calibrate)
 			goto done;
 
+		/* Reduce code size by dropping other methods */
+		if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
+			panic("no timer");
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;
-- 
2.23.0.866.gb869b98d4c-goog