[U-Boot] [PATCH v3 077/108] spi: ich: Move the protection/lockdown code into a function

[Simon Glass]

Reduce the size of the probe function but putting this code into its own
function.

Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 drivers/spi/ich.c | 55 +++++++++++++++++++++++++++++++----------------
 drivers/spi/ich.h |  1 +
 2 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 3eb4599ba27..5b3b3818ded 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -432,6 +432,37 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
 	return 0;
 }
 
+static int ich_protect_lockdown(struct udevice *dev)
+{
+	struct ich_spi_platdata *plat = dev_get_platdata(dev);
+	struct ich_spi_priv *priv = dev_get_priv(dev);
+	int ret = -ENOSYS;
+
+	/* Disable the BIOS write protect so write commands are allowed */
+	if (priv->pch)
+		ret = pch_set_spi_protect(priv->pch, false);
+	if (ret == -ENOSYS) {
+		u8 bios_cntl;
+
+		bios_cntl = ich_readb(priv, priv->bcr);
+		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
+		ich_writeb(priv, bios_cntl, priv->bcr);
+	} else if (ret) {
+		debug("%s: Failed to disable write-protect: err=%d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	/* Lock down SPI controller settings if required */
+	if (plat->lockdown) {
+		ich_spi_config_opcode(dev);
+		spi_lock_down(plat, priv->base);
+	}
+
+	return 0;
+}
+
 static int ich_init_controller(struct udevice *dev,
 			       struct ich_spi_platdata *plat,
 			       struct ich_spi_priv *ctlr)
@@ -497,30 +528,18 @@ static int ich_spi_probe(struct udevice *dev)
 {
 	struct ich_spi_platdata *plat = dev_get_platdata(dev);
 	struct ich_spi_priv *priv = dev_get_priv(dev);
-	uint8_t bios_cntl;
 	int ret;
 
+	/* Find a PCH if there is one */
+	uclass_first_device(UCLASS_PCH, &priv->pch);
+
 	ret = ich_init_controller(dev, plat, priv);
 	if (ret)
 		return ret;
-	/* Disable the BIOS write protect so write commands are allowed */
-	ret = pch_set_spi_protect(dev->parent, false);
-	if (ret == -ENOSYS) {
-		bios_cntl = ich_readb(priv, priv->bcr);
-		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
-		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
-		ich_writeb(priv, bios_cntl, priv->bcr);
-	} else if (ret) {
-		debug("%s: Failed to disable write-protect: err=%d\n",
-		      __func__, ret);
-		return ret;
-	}
 
-	/* Lock down SPI controller settings if required */
-	if (plat->lockdown) {
-		ich_spi_config_opcode(dev);
-		spi_lock_down(plat, priv->base);
-	}
+	ret = ich_protect_lockdown(dev);
+	if (ret)
+		return ret;
 
 	priv->cur_speed = priv->max_speed;
 
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 3dfb2aaff15..77057878a5d 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -191,6 +191,7 @@ struct ich_spi_priv {
 	ulong max_speed;	/* Maximum bus speed in MHz */
 	ulong cur_speed;	/* Current bus speed */
 	struct spi_trans trans;	/* current transaction in progress */
+	struct udevice *pch;	/* PCH, used to control SPI access */
 };
 
 #endif /* _ICH_H_ */
-- 
2.23.0.866.gb869b98d4c-goog