[U-Boot] [PATCH v3 041/108] x86: Reduce mrccache record alignment size
Simon Glass
sjg at chromium.org
Mon Oct 21 03:38:06 UTC 2019
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollolake's 24-byte variable-data record.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/x86/include/asm/mrccache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index 40fda856ff4..abf58182237 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -7,7 +7,7 @@
#ifndef _ASM_MRCCACHE_H
#define _ASM_MRCCACHE_H
-#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_ALIGN 0x100
#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \
('C' << 16) | ('D'<<24))
--
2.23.0.866.gb869b98d4c-goog
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