[U-Boot] [EXT] Re: [PATCH 1/6] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms

Stefan Roese sr at denx.de
Tue Oct 22 15:44:10 UTC 2019

Hi Frieder,

On 22.10.19 16:24, Schrempf Frieder wrote:
> On 22.10.19 15:55, Frieder Schrempf wrote:
>> Hi Stefan,
>> On 22.10.19 15:18, Stefan Roese wrote:
>>> Hi Frieder,
>>> Hi Ashish,
>>> Hi Ye Li,
>>> Hi Fabio,
>>> On 18.09.19 09:42, Stefan Roese wrote:
>>>> Hi Frieder,
>>>> On 18.09.19 09:08, Schrempf Frieder wrote:
>>>> <snip>
>>>>>> One further update on this QSPI driver. This driver only works when
>>>>>> loaded via "imx_usb" on the i.MX6ULL EVK. When programmed into QSPI
>>>>>> and booted from QSPI this driver does not detect the SPI NOR
>>>>>> flash:
>>>>>> => sf probe
>>>>>> unrecognized JEDEC id bytes: ff, ff, ff
>>>>>> Do you have any idea what might explain this difference. I would have
>>>>>> expected that when booting via QSPI it would be "easier" for the
>>>>>> driver, as the BootROM already initializes the QSPI interface. Which
>>>>>> is not the case in the boot via serial download (imx_usb) mode. Here
>>>>>> everyhting (pinmux, clocks, etc) need to be configured.
>>>>>> My feeling is that something is configured "incorrectly" by the
>>>>>> BootROM in this case which is not re-configured as the QSPI driver
>>>>>> needs it to be currently.
>>>>>> Do you have any ideas on what might be the problem here? Is there
>>>>>> something that I can do to help test this? Would it help if I would
>>>>>> send the debug logging of the driver?
>>>>> I have a strong suspicion of what goes wrong in your case. We
>>>>> experienced exactly the same issue recently on i.MX6ULL. For some
>>>>> reasons (I guess differences in BootROM) this does not happen on
>>>>> i.MX6UL.
>>>>> The problem is, that the BootROM sets the TDH bits in the
>>>>> QuadSPI_FLSHCR
>>>>> register to '01' in case it uses the DDR mode. Afterwards when
>>>>> U-Boot or
>>>>> Linux try to access the flash in SDR mode, they fail as the TDH bits
>>>>> are
>>>>> still set. Resetting them to '00' solves the problem.
>>>>> Unfortunately the TDH bits are not documented in the manual of the
>>>>> i.MX6UL/ULL, but they can be found in the manual of the i.MX7.
>>>>> For the QSPI driver, this means it needs a fix to set/reset the TDH
>>>>> bits
>>>>> according to the mode that is used (DDR/SDR).
>>>>> For more details please also look here:
>>>>> https://community.nxp.com/thread/507260
>>>> Perfect. With these bits set to 00 again, booting from QSPI now
>>>> works on the EVK. Many thanks for this hint! :)
>>> I'm coming back to this issue, as we now have the new NXP patches
>>> integrated into mainline. Including this one:
>>> 7949576664ac "spi: fsl_qspi: Fix DDR mode setting for latest iMX
>>> platforms" >
>>> I've now re-tested current mainline on the i.MX6ULL Eval Kit and QSPI
>>> does not work reliably. This is with CONFIG_SYS_FSL_QSPI_AHB enabled
>>> and disabled. How is QSPI supposed to work on i.MX6ULL/ULZ? Is any
>>> one of you running this current mainline driver successfully on one
>>> any i-MX6ULL/ULZ based board? If yes, what is your configuration here?
>> I don't have any experience with the current mainline SPI NOR driver.
> I had a look and the current mainline driver has 7949576664ac "spi:
> fsl_qspi: Fix DDR mode setting for latest iMX platforms", but it still
> does not reset the TDH bits during init, in case the BootROM has left
> them set, which is the case when booting from QSPI on i.MX6ULL.
> Initially for detection the driver does not use DDR, so TDH must be cleared.

I've already "played" with those DDR bits (TDH) in this register -
without success so far.

Let's concentrate on the spi-mem driver instead.


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