[U-Boot] [PATCH] spi: cadence_qspi: support DM_CLK

[Simon Goldschmidt]

On Thu, Oct 24, 2019 at 4:54 AM Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> On Wed, 2019-10-23 at 22:27 +0200, Simon Goldschmidt wrote:
> > Support loading clk speed via DM instead of requiring ad-hoc code.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> > ---
> >
> >  drivers/spi/cadence_qspi.c | 20 ++++++++++++++++++--
> >  1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> > index e2e54cd277..0b89115885 100644
> > --- a/drivers/spi/cadence_qspi.c
> > +++ b/drivers/spi/cadence_qspi.c
> > @@ -5,6 +5,7 @@
> >   */
> >
> >  #include <common.h>
> > +#include <clk.h>
> >  #include <dm.h>
> >  #include <fdtdec.h>
> >  #include <malloc.h>
> > @@ -22,12 +23,27 @@ static int cadence_spi_write_speed(struct udevice
> > *bus, uint hz)
> >  {
> >       struct cadence_spi_platdata *plat = bus->platdata;
> >       struct cadence_spi_priv *priv = dev_get_priv(bus);
> > +     unsigned int ref_clk_hz;
> > +     struct clk clk;
> > +     int ret;
> > +
> > +     ret = clk_get_by_index(bus, 0, &clk);
> > +     if (ret) {
> > +#ifdef CONFIG_CQSPI_REF_CLK
> > +             ref_clk_hz = CONFIG_CQSPI_REF_CLK;
> > +#else
> > +             return ret;
> > +#endif
> > +     } else {
> > +             ref_clk_hz = clk_get_rate(&clk);
> clk_get_rate() might return negative error code if failed to get clock
> rate.

Sigh, you're right. Returning negative error values in an ulong seems like a
funny way of getting people to ignore error values.

I can understand we might have to do that when returning pointers, but this
function should better return long, not ulong...

I'll send a v2.

Regards,
Simon


> > +             clk_free(&clk);
> > +     }
> >
> >       cadence_qspi_apb_config_baudrate_div(priv->regbase,
> > -                                          CONFIG_CQSPI_REF_CLK,
> > hz);
> > +                                          ref_clk_hz, hz);
> >
> >       /* Reconfigure delay timing if speed is changed. */
> > -     cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK,
> > hz,
> > +     cadence_qspi_apb_delay(priv->regbase, ref_clk_hz, hz,
> >                              plat->tshsl_ns, plat->tsd2d_ns,
> >                              plat->tchsh_ns, plat->tslch_ns);
> >