[U-Boot] [PATCH v5 12/19] drivers: Enable cache driver build in SPL

[Ley Foon Tan]

On Wed, Oct 23, 2019 at 2:34 AM Simon Goldschmidt
<simon.k.r.goldschmidt at gmail.com> wrote:
>
> Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
> > Enable cache driver build in SPL.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> > ---
> >   drivers/Makefile | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index a4bb5e4975..0d231cddbb 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
> >   ifndef CONFIG_TPL_BUILD
> >   ifdef CONFIG_SPL_BUILD
> >
> > +obj-$(CONFIG_CACHE) += cache/
>
> Hmm, I'm not sure this can go in via the socfpga tree (in this series).
> Does this change break any existing configs?
Tired to compile Cyclone 5 and Arria 10 platform which enable
CONFIG_L2X0_CACHE, no compilation.
>
> You'd probably have to run this separate from this series so that Tom or
> Simon (Glass) can apply it...?
Okay, I will send this patch separately from this series.

Thanks.
Regards
Ley Foon
>
> >   obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
> >   obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
> >   obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
> >
>