[U-Boot] [PATCH 6/9] phy: atheros: fix delay configuration

[Michael Walle]

The delay_config() code could only set the delay bit. Thus, it could
only enable the delay mode, but not disable it. To make things worse,
the RX delay mode is enabled by default after a hardware reset, so it
could never be disabled. Fix this, by always setting or clearing the
bits. This is also how the linux kernel configures the PHY.

If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.

Signed-off-by: Michael Walle <michael at walle.cc>
---
 drivers/net/phy/atheros.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 4b7a1fb9c4..8bf26626ff 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -78,6 +78,11 @@ static int ar803x_delay_config(struct phy_device *phydev)
 					    0, AR803x_RGMII_TX_CLK_DLY);
 		if (ret < 0)
 			return ret;
+	} else {
+		ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5,
+					    AR803x_RGMII_TX_CLK_DLY, 0);
+		if (ret < 0)
+			return ret;
 	}
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
@@ -86,6 +91,11 @@ static int ar803x_delay_config(struct phy_device *phydev)
 					    0, AR803x_RGMII_RX_CLK_DLY);
 		if (ret < 0)
 			return ret;
+	} else {
+		ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0,
+					    AR803x_RGMII_RX_CLK_DLY, 0);
+		if (ret < 0)
+			return ret;
 	}
 
 	return 0;
-- 
2.20.1