[U-Boot] [RFC PATCH 28/29] octeontx: Add support for OcteonTX SoC platforms
Suneel Garapati
suneelglinux at gmail.com
Tue Oct 29 21:08:20 UTC 2019
From: Suneel Garapati <sgarapati at marvell.com>
This patch adds support for all OcteonTX 81xx/83xx
boards from Marvell.
For 81xx boards, use octeontx_81xx_defconfig and
for 83xx boards, use octeontx_83xx_defconfig.
Signed-off-by: Suneel Garapati <sgarapati at marvell.com>
---
arch/arm/Kconfig | 9 +
arch/arm/Makefile | 1 +
arch/arm/mach-octeontx/Kconfig | 23 +++
arch/arm/mach-octeontx/Makefile | 9 +
arch/arm/mach-octeontx/clock.c | 35 ++++
arch/arm/mach-octeontx/cpu.c | 76 +++++++
arch/arm/mach-octeontx/lowlevel_init.S | 33 +++
board/Marvell/octeontx/Kconfig | 14 ++
board/Marvell/octeontx/MAINTAINERS | 9 +
board/Marvell/octeontx/Makefile | 9 +
board/Marvell/octeontx/board-fdt.c | 271 +++++++++++++++++++++++++
board/Marvell/octeontx/board.c | 137 +++++++++++++
board/Marvell/octeontx/smc.c | 30 +++
board/Marvell/octeontx/soc-utils.c | 53 +++++
configs/octeontx_81xx_defconfig | 133 ++++++++++++
configs/octeontx_83xx_defconfig | 130 ++++++++++++
include/configs/octeontx_common.h | 98 +++++++++
17 files changed, 1070 insertions(+)
create mode 100644 arch/arm/mach-octeontx/Kconfig
create mode 100644 arch/arm/mach-octeontx/Makefile
create mode 100644 arch/arm/mach-octeontx/clock.c
create mode 100644 arch/arm/mach-octeontx/cpu.c
create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S
create mode 100644 board/Marvell/octeontx/Kconfig
create mode 100644 board/Marvell/octeontx/MAINTAINERS
create mode 100644 board/Marvell/octeontx/Makefile
create mode 100644 board/Marvell/octeontx/board-fdt.c
create mode 100644 board/Marvell/octeontx/board.c
create mode 100644 board/Marvell/octeontx/smc.c
create mode 100644 board/Marvell/octeontx/soc-utils.c
create mode 100644 configs/octeontx_81xx_defconfig
create mode 100644 configs/octeontx_83xx_defconfig
create mode 100644 include/configs/octeontx_common.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 629c5e8c2d..ebe180ad90 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1618,6 +1618,13 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply USB_FUNCTION_FASTBOOT
+config ARCH_OCTEONTX
+ bool "Support OcteonTX SoCs"
+ select DM
+ select ARM64
+ select OF_CONTROL
+ select BOARD_LATE_INIT
+ select SYS_CACHE_SHIFT_7
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
@@ -1695,6 +1702,7 @@ source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
+source "arch/arm/mach-octeontx/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
@@ -1772,6 +1780,7 @@ source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
+source "board/Marvell/octeontx/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5384981c17..271ada99e8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -79,6 +79,7 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_TEGRA) += tegra
+machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig
new file mode 100644
index 0000000000..28ecf9821f
--- /dev/null
+++ b/arch/arm/mach-octeontx/Kconfig
@@ -0,0 +1,23 @@
+if ARCH_OCTEONTX
+
+choice
+ prompt "OcteonTX board select"
+ optional
+
+config TARGET_OCTEONTX_81XX
+ bool "Marvell OcteonTX CN81XX"
+
+config TARGET_OCTEONTX_83XX
+ bool "Marvell OcteonTX CN83XX"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "octeontx"
+
+config SYS_PCI_64BIT
+ bool
+ default y
+
+endif
diff --git a/arch/arm/mach-octeontx/Makefile b/arch/arm/mach-octeontx/Makefile
new file mode 100644
index 0000000000..20cb48ad92
--- /dev/null
+++ b/arch/arm/mach-octeontx/Makefile
@@ -0,0 +1,9 @@
+#/* SPDX-License-Identifier: GPL-2.0
+# *
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * https://spdx.org/licenses
+# */
+
+obj-y += lowlevel_init.o clock.o cpu.o
+
diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c
new file mode 100644
index 0000000000..9da21077ec
--- /dev/null
+++ b/arch/arm/mach-octeontx/clock.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/clock.h>
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeontx_get_io_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.pnr_mul * PLL_REF_CLK;
+}
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeontx_get_core_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.c_mul * PLL_REF_CLK;
+}
diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c
new file mode 100644
index 0000000000..9c29c31393
--- /dev/null
+++ b/arch/arm/mach-octeontx/cpu.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OTX_MEM_MAP_USED 3
+
+/* 1 for 83xx, +1 is end of list which needs to be empty */
+#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
+
+static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
+ {
+ .virt = 0x800000000000UL,
+ .phys = 0x800000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x840000000000UL,
+ .phys = 0x840000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x880000000000UL,
+ .phys = 0x880000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }
+
+};
+
+struct mm_region *mem_map = otx_mem_map;
+
+void mem_map_fill(void)
+{
+ int banks = OTX_MEM_MAP_USED;
+ u32 dram_start = CONFIG_SYS_TEXT_BASE;
+
+ if (otx_is_soc(CN83XX)) {
+ otx_mem_map[banks].virt = 0x8c0000000000UL;
+ otx_mem_map[banks].phys = 0x8c0000000000UL;
+ otx_mem_map[banks].size = 0x40000000000UL;
+ otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ otx_mem_map[banks].virt = dram_start;
+ otx_mem_map[banks].phys = dram_start;
+ otx_mem_map[banks].size = gd->ram_size;
+ otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+}
+
+u64 get_page_table_size(void)
+{
+ return 0x80000;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/arch/arm/mach-octeontx/lowlevel_init.S b/arch/arm/mach-octeontx/lowlevel_init.S
new file mode 100644
index 0000000000..41a9f08aed
--- /dev/null
+++ b/arch/arm/mach-octeontx/lowlevel_init.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+.align 8
+.global fdt_base_addr
+fdt_base_addr:
+ .dword 0x0
+
+.global save_boot_params
+save_boot_params:
+ /* Read FDT base from x1 register passed by ATF */
+ adr x21, fdt_base_addr
+ str x1, [x21]
+
+ /* Returns */
+ b save_boot_params_ret
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+ /* any lowlevel init should go here */
+
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
diff --git a/board/Marvell/octeontx/Kconfig b/board/Marvell/octeontx/Kconfig
new file mode 100644
index 0000000000..45d115916c
--- /dev/null
+++ b/board/Marvell/octeontx/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX
+
+config SYS_VENDOR
+ string
+ default "Marvell"
+
+config SYS_BOARD
+ string
+ default "octeontx"
+
+config SYS_CONFIG_NAME
+ default "octeontx_common"
+
+endif
diff --git a/board/Marvell/octeontx/MAINTAINERS b/board/Marvell/octeontx/MAINTAINERS
new file mode 100644
index 0000000000..10816c7a03
--- /dev/null
+++ b/board/Marvell/octeontx/MAINTAINERS
@@ -0,0 +1,9 @@
+OCTEONTX BOARD
+M: Suneel Garapati <sgarapati at marvell.com>
+M: Aaron Williams <awilliams at marvell.com>
+S: Maintained
+F: board/Marvell/octeontx/
+F: include/configs/octeontx_81xx.h
+F: include/configs/octeontx_83xx.h
+F: configs/octeontx_81xx_defconfig
+F: configs/octeontx_83xx_defconfig
diff --git a/board/Marvell/octeontx/Makefile b/board/Marvell/octeontx/Makefile
new file mode 100644
index 0000000000..fbe32ae003
--- /dev/null
+++ b/board/Marvell/octeontx/Makefile
@@ -0,0 +1,9 @@
+#/*
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * SPDX-License-Identifier: GPL-2.0
+# * https://spdx.org/licenses
+# */
+
+obj-y := board.o smc.o soc-utils.o
+obj-$(CONFIG_OF_LIBFDT) += board-fdt.o
diff --git a/board/Marvell/octeontx/board-fdt.c b/board/Marvell/octeontx/board-fdt.c
new file mode 100644
index 0000000000..ec87e0c88a
--- /dev/null
+++ b/board/Marvell/octeontx/board-fdt.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <env.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <asm/arch/board.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern unsigned long fdt_base_addr;
+
+#ifdef CONFIG_NET_OCTEONTX
+static int fdt_get_mdio_bus(const void *fdt, int phy_offset)
+{
+ int node, bus = -1;
+ const u64 *reg;
+ u64 addr;
+
+ if (phy_offset < 0)
+ return -1;
+ /* obtain mdio node and get the reg prop */
+ node = fdt_parent_offset(fdt, phy_offset);
+ if (node < 0)
+ return -1;
+
+ reg = fdt_getprop(fdt, node, "reg", NULL);
+ addr = fdt64_to_cpu(*reg);
+ bus = (addr & (1 << 7)) ? 1 : 0;
+ return bus;
+}
+
+static int fdt_get_phy_addr(const void *fdt, int phy_offset)
+{
+ const u32 *reg;
+ int addr = -1;
+
+ if (phy_offset < 0)
+ return -1;
+ reg = fdt_getprop(fdt, phy_offset, "reg", NULL);
+ addr = fdt32_to_cpu(*reg);
+ return addr;
+}
+
+void fdt_parse_phy_info(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int offset = 0, node, bgx_id = 0, lmacid = 0;
+ const u32 *val;
+ char bgxname[24];
+ int len, rgx_id = 0, eth_id = 0;
+ int phandle, phy_offset;
+ int subnode, i;
+ int bdknode;
+
+ bdknode = fdt_path_offset(fdt, "/cavium,bdk");
+ if (bdknode < 0) {
+ printf("%s: bdk node is missing from device tree: %s\n",
+ __func__, fdt_strerror(bdknode));
+ }
+
+ offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
+ if (offset < 1)
+ return;
+
+ for (bgx_id = 0; bgx_id < MAX_BGX_PER_NODE; bgx_id++) {
+ int phy_addr[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
+ bool autoneg_dis[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+ int mdio_bus[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1};
+ bool lmac_reg[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+ bool lmac_enable[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0};
+
+ snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx_id);
+ node = fdt_subnode_offset(fdt, offset, bgxname);
+ if (node < 0) {
+ /* check if it is rgx node */
+ snprintf(bgxname, sizeof(bgxname), "rgx%d", rgx_id);
+ node = fdt_subnode_offset(fdt, offset, bgxname);
+ if (node < 0) {
+ debug("bgx%d/rgx0 node not found\n", bgx_id);
+ return;
+ }
+ }
+ debug("bgx%d node found\n", bgx_id);
+
+ /*
+ * loop through each of the bgx/rgx nodes
+ * to find PHY nodes
+ */
+ fdt_for_each_subnode(subnode, fdt, node) {
+ /* Check for reg property */
+ val = fdt_getprop(fdt, subnode, "reg", &len);
+ if (val) {
+ debug("lmacid = %d\n", lmacid);
+ lmac_reg[lmacid] = 1;
+ }
+ /* check for phy-handle property */
+ val = fdt_getprop(fdt, subnode, "phy-handle", &len);
+ if (val) {
+ phandle = fdt32_to_cpu(*val);
+ if (!phandle) {
+ debug("phandle not valid %d\n", lmacid);
+ } else {
+ phy_offset = fdt_node_offset_by_phandle
+ (fdt, phandle);
+ phy_addr[lmacid] = fdt_get_phy_addr
+ (fdt, phy_offset);
+ mdio_bus[lmacid] = fdt_get_mdio_bus
+ (fdt, phy_offset);
+ }
+ } else {
+ debug("phy-handle prop not found %d\n",
+ lmacid);
+ }
+ /* check for autonegotiation property */
+ val = fdt_getprop(fdt, subnode,
+ "cavium,disable-autonegotiation",
+ &len);
+ if (val)
+ autoneg_dis[lmacid] = 1;
+
+ eth_id++;
+ lmacid++;
+ }
+
+ for (i = 0; i < MAX_LMAC_PER_BGX; i++) {
+ const char *str;
+
+ snprintf(bgxname, sizeof(bgxname),
+ "BGX-ENABLE.N0.BGX%d.P%d", bgx_id, i);
+ if (bdknode >= 0) {
+ str = fdt_getprop(fdt, bdknode,
+ bgxname, &len);
+ if (str)
+ lmac_enable[i] =
+ simple_strtol(str, NULL,
+ 10);
+ }
+ }
+
+ lmacid = 0;
+ bgx_set_board_info(bgx_id, mdio_bus, phy_addr,
+ autoneg_dis, lmac_reg, lmac_enable);
+ }
+}
+#endif
+
+const char *fdt_get_board_model(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int ret, node, len = 16;
+ const char *str = NULL;
+
+ if (!fdt) {
+ printf("ERROR: %s: no valid device tree found\n", __func__);
+ return NULL;
+ }
+
+ ret = fdt_check_header(fdt);
+ if (ret < 0) {
+ printf("fdt: %s\n", fdt_strerror(ret));
+ return NULL;
+ }
+
+ node = fdt_path_offset(fdt, "/cavium,bdk");
+ if (node < 0) {
+ printf("%s: /cavium,bdk is missing from device tree: %s\n",
+ __func__, fdt_strerror(node));
+ return NULL;
+ }
+
+ str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
+ if (!str)
+ printf("Error: cannot retrieve board model from fdt\n");
+ return str;
+}
+
+void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *mac = NULL;
+ int offset = 0, node, len;
+ int subnode, i = 0;
+ char bgxname[24];
+
+ offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge");
+ if (offset < 0) {
+ printf("%s couldn't find mrml bridge node in fdt\n",
+ __func__);
+ return;
+ }
+ if (bgx == 2 && otx_is_soc(CN81XX)) {
+ snprintf(bgxname, sizeof(bgxname), "rgx%d", 0);
+ lmac = 0;
+ } else {
+ snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx);
+ }
+
+ node = fdt_subnode_offset(fdt, offset, bgxname);
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ if (i++ != lmac)
+ continue;
+ /* check for local-mac-address */
+ mac = fdt_getprop(fdt, subnode, "local-mac-address", &len);
+ if (mac) {
+ debug("%s mac %pM\n", __func__, mac);
+ memcpy(eth, mac, ARP_HLEN);
+ } else {
+ memset(eth, 0, ARP_HLEN);
+ }
+ debug("%s eth %pM\n", __func__, eth);
+ return;
+ }
+}
+
+int arch_fixup_memory_node(void *blob)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* remove "cavium, bdk" node from DT */
+ int ret = 0, offset;
+
+ ret = fdt_check_header(blob);
+ if (ret < 0) {
+ printf("ERROR: %s\n", fdt_strerror(ret));
+ return ret;
+ }
+
+ if (blob) {
+ offset = fdt_path_offset(blob, "/cavium,bdk");
+ if (offset < 0) {
+ printf("ERROR: FDT BDK node not found\n");
+ return offset;
+ }
+
+ /* delete node */
+ ret = fdt_del_node(blob, offset);
+ if (ret < 0) {
+ printf("WARNING : could not remove bdk node\n");
+ return ret;
+ }
+
+ debug("%s deleted bdk node\n", __func__);
+ }
+
+ return 0;
+}
+
+/**
+ * Return the FDT base address that was passed by ATF
+ *
+ * @return FDT base address received from ATF in x1 register
+ */
+void *board_fdt_blob_setup(void)
+{
+ return (void *)fdt_base_addr;
+}
diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c
new file mode 100644
index 0000000000..e7646bcaf1
--- /dev/null
+++ b/board/Marvell/octeontx/board.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+extern unsigned long fdt_base_addr;
+
+void octeontx_cleanup_ethaddr(void)
+{
+ char ename[32];
+
+ for (int i = 0; i < 20; i++) {
+ sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
+ if (env_get(ename))
+ env_set(ename, NULL);
+ }
+}
+
+int octeontx_board_has_pmp(void)
+{
+ return (otx_is_board("sff8104") || otx_is_board("nas8104"));
+}
+
+int board_early_init_r(void)
+{
+ pci_init();
+ return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_NET_OCTEONTX
+ fdt_parse_phy_info();
+#endif
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = smc_dram_size(0);
+ gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+
+ mem_map_fill();
+
+ return 0;
+}
+
+#ifdef CONFIG_NET_OCTEONTX
+void board_late_probe_devices(void)
+{
+ struct udevice *dev;
+ int err, bgx_cnt, i;
+
+ /* Probe MAC(BGX) and NIC PF devices before Network stack init */
+ bgx_cnt = otx_is_soc(CN81XX) ? 2 : 4;
+ for (i = 0; i < bgx_cnt; i++) {
+ err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, 0xA026, i,
+ &dev);
+ if (err)
+ debug("%s BGX%d device not found\n", __func__, i);
+ }
+ if (otx_is_soc(CN81XX)) {
+ err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, 0xA054, 0,
+ &dev);
+ if (err)
+ debug("%s RGX device not found\n", __func__);
+ }
+ err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, 0xA01E, 0, &dev);
+ if (err)
+ debug("NIC PF device not found\n");
+}
+#endif
+
+/**
+ * Board late initialization routine.
+ */
+int board_late_init(void)
+{
+ char boardname[32];
+
+ /*
+ * Try to cleanup ethaddr env variables, this is needed
+ * as with each boot, configuration of network interfaces can change.
+ */
+ octeontx_cleanup_ethaddr();
+
+ snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
+ env_set("prompt", boardname);
+
+ set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
+
+#ifdef CONFIG_NET_OCTEONTX
+ board_late_probe_devices();
+#endif
+ return 0;
+}
+
+/*
+ * Invoked before relocation, so limit to stack variables.
+ */
+int show_board_info(void)
+{
+ char *str = NULL;
+
+ if (otx_is_soc(CN81XX))
+ str = "CN81XX";
+ if (otx_is_soc(CN83XX))
+ str = "CN83XX";
+ printf("OcteonTX %s ARM V8 Core\n", str);
+
+ printf("Board: %s\n", fdt_get_board_model());
+
+ return 0;
+}
+
diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c
new file mode 100644
index 0000000000..f6e6706b57
--- /dev/null
+++ b/board/Marvell/octeontx/smc.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/system.h>
+#include <asm/arch/smc.h>
+
+#include <asm/psci.h>
+
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t smc_dram_size(unsigned int node)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = OCTEONTX_DRAM_SIZE;
+ regs.regs[1] = node;
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
diff --git a/board/Marvell/octeontx/soc-utils.c b/board/Marvell/octeontx/soc-utils.c
new file mode 100644
index 0000000000..f84ac09a8b
--- /dev/null
+++ b/board/Marvell/octeontx/soc-utils.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+int read_platform(void)
+{
+ int plat = PLATFORM_HW;
+
+ const char *model = fdt_get_board_model();
+
+ if (model && !strncmp(model, "ASIM-", 5))
+ plat = PLATFORM_ASIM;
+ if (model && !strncmp(model, "EMUL-", 5))
+ plat = PLATFORM_EMULATOR;
+ return plat;
+}
+
+static inline u64 read_midr(void)
+{
+ u64 result;
+
+ asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
+ return result;
+}
+
+u8 read_partnum(void)
+{
+ return ((read_midr() >> 4) & 0xFF);
+}
+
+const char *read_board_name(void)
+{
+ return fdt_get_board_model();
+}
+
+bool read_alt_pkg(void)
+{
+ return false;
+}
+
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
new file mode 100644
index 0000000000..39c9fbc148
--- /dev/null
+++ b/configs/octeontx_81xx_defconfig
@@ -0,0 +1,133 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_OCTEONTX=y
+CONFIG_SYS_TEXT_BASE=0x500000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_OCTEONTX_81XX=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x87e028000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=4 rootwait rw root=/dev/sda2 coherent_pool=16M"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Marvell> "
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=16000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OCTEONTX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_OCTEONTX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=16000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_E1000_SPI=y
+CONFIG_CMD_E1000=y
+CONFIG_NET_OCTEONTX=y
+CONFIG_OCTEONTX_SMI=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_OCTEONTX=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1337=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OCTEONTX_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_WDT=y
+CONFIG_FAT_WRITE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
new file mode 100644
index 0000000000..00eb039de8
--- /dev/null
+++ b/configs/octeontx_83xx_defconfig
@@ -0,0 +1,130 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_OCTEONTX=y
+CONFIG_SYS_TEXT_BASE=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_OCTEONTX_83XX=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x87e028000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/sda2 coherent_pool=16M"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Marvell> "
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=16000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OCTEONTX=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=16000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_E1000_SPI=y
+CONFIG_CMD_E1000=y
+CONFIG_NET_OCTEONTX=y
+CONFIG_OCTEONTX_SMI=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_OCTEONTX=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1337=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_PL011=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OCTEONTX_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_WDT=y
+CONFIG_FAT_WRITE=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h
new file mode 100644
index 0000000000..46134bb321
--- /dev/null
+++ b/include/configs/octeontx_common.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __OCTEONTX_COMMON_H__
+#define __OCTEONTX_COMMON_H__
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/** Maximum size of image supported for bootm (and bootable FIT images) */
+#define CONFIG_SYS_BOOTM_LEN (256 << 20)
+
+/** Memory base address */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE
+
+/** Stack starting address */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
+
+/** Memory test starting address */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+
+/** Memory test end address */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0xf0000)
+
+/** Heap size for U-Boot */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+/* Allow environment variable to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/** Reduce hashes printed out */
+#define CONFIG_TFTP_TSIZE
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* AHCI support Definitions */
+#ifdef CONFIG_DM_SCSI
+/** Maximum number of SATA devices per controller*/
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+/** Enable 48-bit SATA addressing */
+# define CONFIG_LBA48
+/** Enable 64-bit addressing */
+# define CONFIG_SYS_64BIT_LBA
+#endif
+
+/***** SPI Defines *********/
+#ifdef CONFIG_DM_SPI_FLASH
+# define CONFIG_SF_DEFAULT_BUS 0
+# define CONFIG_SF_DEFAULT_CS 0
+#endif
+
+/** Extra environment settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=040080000\0" \
+ "autoload=0\0"
+
+/** Environment defines */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_OFFSET 0xf00000
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MAXARGS 64 /** max command args */
+
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8191
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT env_get("prompt")
+
+/** EMMC specific defines */
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_CMD_BKOPS_ENABLE
+
+#if defined(CONFIG_NAND_OCTEONTX)
+#define CONFIG_MTD_DEVICE
+/*#define CONFIG_MTD_CONCAT */
+#define CONFIG_SYS_MAX_NAND_DEVICE 8
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+#endif /* __OCTEONTX_COMMON_H__ */
--
2.23.0
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