[U-Boot] [PATCH 1/8] riscv: ax25: add SPL support

[Bin Meng]

Hi Rick,

On Wed, Oct 30, 2019 at 8:42 AM Rick Chen <rickchen36 at gmail.com> wrote:
>
> Hi Bin
>
> >
> > Hi Rick,
> >
> > On Fri, Oct 25, 2019 at 2:17 PM Andes <uboot at andestech.com> wrote:
> > >
> > > From: Rick Chen <rick at andestech.com>
> > >
> > > The U-Boot SPL will boot in M mode and load the
> > > FIT image which include OpenSbi and U-Boot proper
> >
> > nits: OpenSBI
>
> OK
>
> >
> > > images. After loading progress, it will jump to
> > > OpenSbi first and then U-Boot proper which will
> >
> > ditto
>
> OK
>
> >
> > > run in S mode.
> > >
> > > Signed-off-by: Rick Chen <rick at andestech.com>
> > > Cc: KC Lin <kclin at andestech.com>
> > > Cc: Alan Kao <alankao at andestech.com>
> > > ---
> > >  arch/riscv/cpu/ax25/Kconfig | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
> > > index d411a79..8d8d71d 100644
> > > --- a/arch/riscv/cpu/ax25/Kconfig
> > > +++ b/arch/riscv/cpu/ax25/Kconfig
> > > @@ -6,7 +6,9 @@ config RISCV_NDS
> > >         imply RISCV_TIMER
> > >         imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
> > >         imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
> > > -       imply V5L2_CACHE
> >
> > Why this is removed?
>
> Without CACHE_SUPPORT, the compiling will fail while enable V5l2_CACHE.
> That is why I remove it. I hope it can be enable manually.
> Because it will enlarge U-Boot SPL size.
>

Could you please describe it in the commit message?

Regards,
Bin