[U-Boot] [PATCH 7/8] riscv: Fix clear bss loop in the start-up code

[Rick Chen]

Hi Bin

>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes <uboot at andestech.com> wrote:
> >
> > From: Rick Chen <rick at andestech.com>
> >
> > For RV64, it will use sd instruction to clear t0
> > register, and the increament will be 8 bytes. So
> > if the difference between__bss_strat and __bss_end
> > was not 8 bytes aligned, the clear bss loop will
> > overflow and acks like system hang.
> >
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > Cc: KC Lin <kclin at andestech.com>
> > Cc: Alan Kao <alankao at andestech.com>
> > ---
> >  arch/riscv/cpu/start.S | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > index 0a2ce6d..ee6d471 100644
> > --- a/arch/riscv/cpu/start.S
> > +++ b/arch/riscv/cpu/start.S
> > @@ -174,7 +174,7 @@ spl_clear_bss:
> >  spl_clear_bss_loop:
> >         SREG    zero, 0(t0)
> >         addi    t0, t0, REGBYTES
> > -       bne     t0, t1, spl_clear_bss_loop
> > +       blt     t0, t1, spl_clear_bss_loop
>
> This leaves bss section not completely zeroed.

I don't think this will clear bss section incompletely.
Can you check it again ?
Or explain more details why you think so ?

Thanks
Rick


>
> >
> >  spl_stack_gd_setup:
> >         jal     spl_relocate_stack_gd
> > @@ -324,7 +324,7 @@ clear_bss:
> >  clbss_l:
> >         SREG    zero, 0(t0)             /* clear loop... */
> >         addi    t0, t0, REGBYTES
> > -       bne     t0, t1, clbss_l
> > +       blt     t0, t1, clbss_l
> >
> >  relocate_secondary_harts:
> >  #ifdef CONFIG_SMP
> > --
>
> Regards,
> Bin