[U-Boot] [PATCH v2 06/14] DM: eth: Switch display5 board to use DM_ETH

Lukasz Majewski lukma at denx.de
Tue Sep 3 14:38:42 UTC 2019


After this commit the display5 device would use FEC driver supporting
driver model (DM_ETH).

Signed-off-by: Lukasz Majewski <lukma at denx.de>

---

Changes in v2:
- Use dm_gpio* functions instead of gpio_* ones

 arch/arm/mach-imx/mx6/Kconfig      |   1 +
 board/liebherr/display5/display5.c | 134 +++++++++----------------------------
 include/configs/display5.h         |   8 ---
 3 files changed, 31 insertions(+), 112 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 2496ecacb104..aef18726702b 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -187,6 +187,7 @@ config TARGET_DHCOMIMX6
 config TARGET_DISPLAY5
 	bool "LWN DISPLAY5 board"
 	select DM
+	select DM_ETH
 	select DM_I2C
 	select DM_MMC
 	select DM_GPIO
diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c
index 0cc77dac0fa1..e008ea9a3fb8 100644
--- a/board/liebherr/display5/display5.c
+++ b/board/liebherr/display5/display5.c
@@ -155,130 +155,42 @@ static void displ5_setup_ecspi(void)
 		gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
 }
 
-#ifdef CONFIG_FEC_MXC
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-
-	/* for old evalboard with R159 present and R160 not populated */
-	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(NO_PAD_CTRL),
-
-	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-
-	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/*INT#_GBE*/
-	MX6_PAD_ENET_TX_EN__GPIO1_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
+/*
+ * Do not overwrite the console
+ * Always use serial for U-Boot console
+ */
+int overwrite_console(void)
 {
-	SETUP_IOMUX_PADS(enet_pads);
-	gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
+	return 1;
 }
 
-static int setup_mac_from_fuse(void)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
 {
-	unsigned char enetaddr[6];
-	int ret;
-
-	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
-	if (ret)	/* ethaddr is already set */
-		return 0;
-
-	imx_get_mac_from_fuse(0, enetaddr);
-
-	if (is_valid_ethaddr(enetaddr)) {
-		eth_env_set_enetaddr("ethaddr", enetaddr);
-		return 0;
-	}
-
+	fdt_fixup_ethernet(blob);
 	return 0;
 }
+#endif
 
-int board_eth_init(bd_t *bd)
+int board_phy_config(struct phy_device *phydev)
 {
-	struct phy_device *phydev;
-	struct mii_dev *bus;
-	int ret;
-
-	setup_iomux_enet();
-
-	iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
-
-	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
-	if (ret)
-		return ret;
-
-	setup_mac_from_fuse();
-
-	bus = fec_get_miibus(IMX_FEC_BASE, -1);
-	if (!bus)
-		return -ENODEV;
-
-	/*
-	 * We use here the "rgmii-id" mode of operation and allow M88E1512
-	 * PHY to use its internally callibrated RX/TX delays
-	 */
-	phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
-				  PHY_INTERFACE_MODE_RGMII_ID);
-	if (!phydev) {
-		ret = -ENODEV;
-		goto err_phy;
-	}
-
 	/* display5 due to PCB routing can only work with 100 Mbps */
 	phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
 				 ADVERTISED_1000baseX_Full |
 				 SUPPORTED_1000baseT_Half |
 				 SUPPORTED_1000baseT_Full);
 
-	ret  = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
-	if (ret)
-		goto err_sw;
-
-	return 0;
-
-err_sw:
-	free(phydev);
-err_phy:
-	mdio_unregister(bus);
-	free(bus);
-	return ret;
-}
-#endif /* CONFIG_FEC_MXC */
-
-/*
- * Do not overwrite the console
- * Always use serial for U-Boot console
- */
-int overwrite_console(void)
-{
-	return 1;
-}
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	fdt_fixup_ethernet(blob);
 	return 0;
 }
-#endif
 
 int board_init(void)
 {
+	struct gpio_desc phy_int_gbe;
+	int ret;
+
 	debug("board init\n");
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
@@ -288,6 +200,7 @@ int board_init(void)
 
 	displ5_setup_ecspi();
 
+	/* Setup misc (application specific) stuff */
 	SETUP_IOMUX_PADS(misc_pads);
 
 	get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
@@ -303,6 +216,19 @@ int board_init(void)
 
 	udelay(25);
 
+	/* Setup low level FEC (ETH) */
+	ret = dm_gpio_lookup_name("GPIO1_28", &phy_int_gbe);
+	if (ret) {
+		printf("Cannot get GPIO1_28\n");
+	} else {
+		ret = dm_gpio_request(&phy_int_gbe, "INT_GBE");
+		if (!ret)
+			dm_gpio_set_dir_flags(&phy_int_gbe, GPIOD_IS_IN);
+	}
+
+	iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
+	enable_fec_anatop_clock(0, ENET_125MHZ);
+
 	return 0;
 }
 
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 2a039c24288f..15027f153341 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -59,14 +59,6 @@
 /* I2C Configs */
 #define CONFIG_I2C_MULTI_BUS
 
-/* Ethernet */
-#ifdef CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_ETHPRIME			"FEC"
-#define CONFIG_FEC_MXC_PHYADDR		0
-#endif
-
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	2
-- 
2.11.0



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