[U-Boot] [PATCHv2] armv8: ls1028a: Updated lane C configuration to PCIe2 for 0x13BB

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIe1, so fix it.

Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - Fixed a typo in changelog.

 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
index 5835a3a69e..313f3f1e8a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -24,7 +24,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
 	{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
-	{0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
+	{0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
 	{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
 	{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
 	{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
-- 
2.17.1