[U-Boot] [PATCH v2 15/26] arm: dts: k3-j721e-main: Add C71x DSP node

[Lokesh Vutla]

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

Signed-off-by: Suman Anna <s-anna at ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
 arch/arm/dts/k3-j721e-common-proc-board.dts |  1 +
 arch/arm/dts/k3-j721e-main.dtsi             | 11 +++++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index a548277718..b21f597a80 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -22,6 +22,7 @@
 		remoteproc5 = &main_r5fss1_core1;
 		remoteproc6 = &c66_0;
 		remoteproc7 = &c66_1;
+		remoteproc8 = &c71_0;
 	};
 };
 
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index c3aa0cdcf1..6bd59bac52 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -328,4 +328,15 @@
 		ti,sci-proc-ids = <0x04 0xFF>;
 		resets = <&k3_reset 143 1>;
 	};
+
+	c71_0: dsp at 64800000 {
+		compatible = "ti,j721e-c71-dsp";
+		reg = <0x00 0x64800000 0x00 0x00080000>,
+		      <0x00 0x64e00000 0x00 0x0000c000>;
+		reg-names = "l2sram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <15>;
+		ti,sci-proc-ids = <0x30 0xFF>;
+		resets = <&k3_reset 15 1>;
+	};
 };
-- 
2.22.0