[U-Boot] [v3, 2/4] mmc: fsl_esdhc: clean up code
Yangbo Lu
yangbo.lu at nxp.com
Wed Sep 11 02:43:58 UTC 2019
This patch is just to clean up code. There were not changes on function.
Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
---
Changes for v2:
- Involved esdhc_ops in non-DM conditional build.
Changes for v3:
- None.
---
drivers/mmc/fsl_esdhc.c | 286 ++++++++++++++++++++++++------------------------
include/fsl_esdhc.h | 203 ++++++++++++++++------------------
2 files changed, 238 insertions(+), 251 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ff5565c..3b079f1 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -25,12 +25,13 @@
DECLARE_GLOBAL_DATA_PTR;
-#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
- IRQSTATEN_CINT | \
- IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
- IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
- IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
- IRQSTATEN_DINT)
+#define ESDHC_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
+ IRQSTATEN_DINT | IRQSTATEN_BWR | \
+ IRQSTATEN_BRR | IRQSTATEN_CINT | \
+ IRQSTATEN_CTOE | IRQSTATEN_CCE | \
+ IRQSTATEN_CEBE | IRQSTATEN_CIE | \
+ IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+ IRQSTATEN_DEBE)
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
@@ -76,16 +77,15 @@ struct fsl_esdhc_plat {
* struct fsl_esdhc_priv
*
* @esdhc_regs: registers of the sdhc controller
- * @sdhc_clk: Current clk of the sdhc controller
+ * @sdhc_clk: reference clk of the sdhc controller
+ * @per_clk: peripheral clock
+ * @clock: target clock
* @bus_width: bus width, 1bit, 4bit or 8bit
- * @cfg: mmc config
* @mmc: mmc
* Following is used when Driver Model is enabled for MMC
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @cd_gpio: gpio for card detection
- * @wp_gpio: gpio for write protection
*/
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
@@ -102,7 +102,7 @@ struct fsl_esdhc_priv {
};
/* Return the XFERTYP flags for a given command and data packet */
-static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+static uint esdhc_setup_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
uint xfertyp = 0;
@@ -310,9 +310,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
return 0;
}
-static void check_and_invalidate_dcache_range
- (struct mmc_cmd *cmd,
- struct mmc_data *data) {
+static void esdhc_invalidate_dcache_range(struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
unsigned start = 0;
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
@@ -377,11 +377,11 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
return err;
if (data->flags & MMC_DATA_READ)
- check_and_invalidate_dcache_range(cmd, data);
+ esdhc_invalidate_dcache_range(cmd, data);
}
/* Figure out the transfer arguments */
- xfertyp = esdhc_xfertyp(cmd, data);
+ xfertyp = esdhc_setup_xfertyp(cmd, data);
/* Mask all irqs */
esdhc_write32(®s->irqsigen, 0);
@@ -479,7 +479,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
* speculative pre-fetching etc.
*/
if (data->flags & MMC_DATA_READ) {
- check_and_invalidate_dcache_range(cmd, data);
+ esdhc_invalidate_dcache_range(cmd, data);
}
#endif
}
@@ -506,7 +506,8 @@ out:
return err;
}
-static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
+static void esdhc_set_clock(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
@@ -581,7 +582,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#endif
/* Set the clock speed */
if (priv->clock != mmc->clock)
- set_sysctl(priv, mmc, mmc->clock);
+ esdhc_set_clock(priv, mmc, mmc->clock);
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
@@ -670,41 +671,7 @@ static int esdhc_reset(struct fsl_esdhc *regs)
}
#if !CONFIG_IS_ENABLED(DM_MMC)
-static int esdhc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_getcd_common(priv);
-}
-
-static int esdhc_init(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_init_common(priv, mmc);
-}
-
-static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_send_cmd_common(priv, mmc, cmd, data);
-}
-
-static int esdhc_set_ios(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_set_ios_common(priv, mmc);
-}
-
-static const struct mmc_ops esdhc_ops = {
- .getcd = esdhc_getcd,
- .init = esdhc_init,
- .send_cmd = esdhc_send_cmd,
- .set_ios = esdhc_set_ios,
-};
+static const struct mmc_ops esdhc_ops;
#endif
static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
@@ -728,7 +695,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
SYSCTL_IPGEN | SYSCTL_CKEN);
- writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
+ writel(ESDHC_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
#ifndef CONFIG_DM_MMC
memset(cfg, '\0', sizeof(*cfg));
@@ -738,20 +705,19 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
caps = esdhc_read32(®s->hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
- caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
- ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+ caps = caps & ~(HOSTCAPBLT2_SRS | HOSTCAPBLT2_VS18 | HOSTCAPBLT2_VS30);
#endif
/* T4240 host controller capabilities register should have VS33 bit */
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- caps = caps | ESDHC_HOSTCAPBLT_VS33;
+ caps = caps | HOSTCAPBLT2_VS33;
#endif
- if (caps & ESDHC_HOSTCAPBLT_VS18)
+ if (caps & HOSTCAPBLT2_VS18)
voltage_caps |= MMC_VDD_165_195;
- if (caps & ESDHC_HOSTCAPBLT_VS30)
+ if (caps & HOSTCAPBLT2_VS30)
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
- if (caps & ESDHC_HOSTCAPBLT_VS33)
+ if (caps & HOSTCAPBLT2_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->name = "FSL_SDHC";
@@ -785,7 +751,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
cfg->host_caps &= ~MMC_MODE_4BIT;
}
- if (caps & ESDHC_HOSTCAPBLT_HSS)
+ if (caps & HOSTCAPBLT2_HSS)
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
@@ -801,76 +767,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
- struct fsl_esdhc_priv *priv)
-{
- if (!cfg || !priv)
- return -EINVAL;
-
- priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
- priv->bus_width = cfg->max_bus_width;
- priv->sdhc_clk = cfg->sdhc_clk;
- priv->wp_enable = cfg->wp_enable;
-
- return 0;
-};
-
-int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
-{
- struct fsl_esdhc_plat *plat;
- struct fsl_esdhc_priv *priv;
- struct mmc *mmc;
- int ret;
-
- if (!cfg)
- return -EINVAL;
-
- priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
- if (!priv)
- return -ENOMEM;
- plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
- if (!plat) {
- free(priv);
- return -ENOMEM;
- }
-
- ret = fsl_esdhc_cfg_to_priv(cfg, priv);
- if (ret) {
- debug("%s xlate failure\n", __func__);
- free(plat);
- free(priv);
- return ret;
- }
-
- ret = fsl_esdhc_init(priv, plat);
- if (ret) {
- debug("%s init failure\n", __func__);
- free(plat);
- free(priv);
- return ret;
- }
-
- mmc = mmc_create(&plat->cfg, priv);
- if (!mmc)
- return -EIO;
-
- priv->mmc = mmc;
-
- return 0;
-}
-
-int fsl_esdhc_mmc_init(bd_t *bis)
-{
- struct fsl_esdhc_cfg *cfg;
-
- cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->arch.sdhc_clk;
- return fsl_esdhc_initialize(bis, cfg);
-}
-#endif
-
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
void mmc_adapter_card_type_ident(void)
{
@@ -944,7 +840,115 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
-#if CONFIG_IS_ENABLED(DM_MMC)
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+ .getcd = esdhc_getcd,
+ .init = esdhc_init,
+ .send_cmd = esdhc_send_cmd,
+ .set_ios = esdhc_set_ios,
+};
+
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+
+ return 0;
+};
+
+/* eSDHC initialization requiring cfg */
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_plat *plat;
+ struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+/* eSDHC complete initialization */
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+ struct fsl_esdhc_cfg *cfg;
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
+ return fsl_esdhc_initialize(bis, cfg);
+}
+
+#else /* DM_MMC */
+
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
@@ -1068,13 +1072,13 @@ static int fsl_esdhc_bind(struct udevice *dev)
}
U_BOOT_DRIVER(fsl_esdhc) = {
- .name = "fsl-esdhc-mmc",
- .id = UCLASS_MMC,
- .of_match = fsl_esdhc_ids,
- .ops = &fsl_esdhc_ops,
- .bind = fsl_esdhc_bind,
- .probe = fsl_esdhc_probe,
- .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
- .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .ops = &fsl_esdhc_ops,
+ .bind = fsl_esdhc_bind,
+ .probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
#endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 7d7e946..e18044b 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -19,101 +19,19 @@
#include "../board/freescale/common/qixis.h"
#endif
-/* FSL eSDHC-specific constants */
-#define SYSCTL 0x0002e02c
-#define SYSCTL_INITA 0x08000000
-#define SYSCTL_TIMEOUT_MASK 0x000f0000
-#define SYSCTL_CLOCK_MASK 0x0000fff0
-#define SYSCTL_CKEN 0x00000008
-#define SYSCTL_PEREN 0x00000004
-#define SYSCTL_HCKEN 0x00000002
-#define SYSCTL_IPGEN 0x00000001
-#define SYSCTL_RSTA 0x01000000
-#define SYSCTL_RSTC 0x02000000
-#define SYSCTL_RSTD 0x04000000
-
-#define IRQSTAT 0x0002e030
-#define IRQSTAT_DMAE (0x10000000)
-#define IRQSTAT_AC12E (0x01000000)
-#define IRQSTAT_DEBE (0x00400000)
-#define IRQSTAT_DCE (0x00200000)
-#define IRQSTAT_DTOE (0x00100000)
-#define IRQSTAT_CIE (0x00080000)
-#define IRQSTAT_CEBE (0x00040000)
-#define IRQSTAT_CCE (0x00020000)
-#define IRQSTAT_CTOE (0x00010000)
-#define IRQSTAT_CINT (0x00000100)
-#define IRQSTAT_CRM (0x00000080)
-#define IRQSTAT_CINS (0x00000040)
-#define IRQSTAT_BRR (0x00000020)
-#define IRQSTAT_BWR (0x00000010)
-#define IRQSTAT_DINT (0x00000008)
-#define IRQSTAT_BGE (0x00000004)
-#define IRQSTAT_TC (0x00000002)
-#define IRQSTAT_CC (0x00000001)
-
-#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
-#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
- IRQSTAT_DMAE)
-#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
-
-#define IRQSTATEN 0x0002e034
-#define IRQSTATEN_DMAE (0x10000000)
-#define IRQSTATEN_AC12E (0x01000000)
-#define IRQSTATEN_DEBE (0x00400000)
-#define IRQSTATEN_DCE (0x00200000)
-#define IRQSTATEN_DTOE (0x00100000)
-#define IRQSTATEN_CIE (0x00080000)
-#define IRQSTATEN_CEBE (0x00040000)
-#define IRQSTATEN_CCE (0x00020000)
-#define IRQSTATEN_CTOE (0x00010000)
-#define IRQSTATEN_CINT (0x00000100)
-#define IRQSTATEN_CRM (0x00000080)
-#define IRQSTATEN_CINS (0x00000040)
-#define IRQSTATEN_BRR (0x00000020)
-#define IRQSTATEN_BWR (0x00000010)
-#define IRQSTATEN_DINT (0x00000008)
-#define IRQSTATEN_BGE (0x00000004)
-#define IRQSTATEN_TC (0x00000002)
-#define IRQSTATEN_CC (0x00000001)
-
-#define ESDHCCTL 0x0002e40c
-#define ESDHCCTL_PCS (0x00080000)
-
-#define PRSSTAT 0x0002e024
-#define PRSSTAT_DAT0 (0x01000000)
-#define PRSSTAT_CLSL (0x00800000)
-#define PRSSTAT_WPSPL (0x00080000)
-#define PRSSTAT_CDPL (0x00040000)
-#define PRSSTAT_CINS (0x00010000)
-#define PRSSTAT_BREN (0x00000800)
-#define PRSSTAT_BWEN (0x00000400)
-#define PRSSTAT_SDSTB (0X00000008)
-#define PRSSTAT_DLA (0x00000004)
-#define PRSSTAT_CICHB (0x00000002)
-#define PRSSTAT_CIDHB (0x00000001)
-
-#define PROCTL 0x0002e028
-#define PROCTL_INIT 0x00000020
-#define PROCTL_DTW_4 0x00000002
-#define PROCTL_DTW_8 0x00000004
-#define PROCTL_D3CD 0x00000008
-
-#define CMDARG 0x0002e008
-
-#define XFERTYP 0x0002e00c
+/* eSDHC_XFERTYP register: 0x0000000c */
#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
-#define XFERTYP_CMDTYP_NORMAL 0x0
-#define XFERTYP_CMDTYP_SUSPEND 0x00400000
-#define XFERTYP_CMDTYP_RESUME 0x00800000
#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_NORMAL 0x00000000
#define XFERTYP_DPSEL 0x00200000
#define XFERTYP_CICEN 0x00100000
#define XFERTYP_CCCEN 0x00080000
-#define XFERTYP_RSPTYP_NONE 0
-#define XFERTYP_RSPTYP_136 0x00010000
-#define XFERTYP_RSPTYP_48 0x00020000
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_NONE 0x00000000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
#define XFERTYP_DDREN 0x00000008
@@ -121,20 +39,84 @@
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001
-#define CINS_TIMEOUT 1000
-#define PIO_TIMEOUT 500
+/* eSDHC_PRSSTAT register: 0x00000024 */
+#define PRSSTAT_DAT0 0x01000000
+#define PRSSTAT_CLSL 0x00800000
+#define PRSSTAT_WPSPL 0x00080000
+#define PRSSTAT_CDPL 0x00040000
+#define PRSSTAT_CINS 0x00010000
+#define PRSSTAT_BREN 0x00000800
+#define PRSSTAT_BWEN 0x00000400
+#define PRSSTAT_SDSTB 0X00000008
+#define PRSSTAT_DLA 0x00000004
+#define PRSSTAT_CICHB 0x00000002
+#define PRSSTAT_CIDHB 0x00000001
+
+/* eSDHC_PROCTL register: 0x00000028 */
+#define PROCTL_INIT 0x00000020
+#define PROCTL_D3CD 0x00000008
+#define PROCTL_DTW_8 0x00000004
+#define PROCTL_DTW_4 0x00000002
-#define DSADDR 0x2e004
+/* eSDHC_SYSCTL register: 0x0000002c */
+#define SYSCTL_INITA 0x08000000
+#define SYSCTL_RSTD 0x04000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_CKEN 0x00000008
+#define SYSCTL_PEREN 0x00000004
+#define SYSCTL_HCKEN 0x00000002
+#define SYSCTL_IPGEN 0x00000001
+#define SYSCTL_TIMEOUT_MASK 0x000f0000
+#define SYSCTL_CLOCK_MASK 0x0000fff0
-#define CMDRSP0 0x2e010
-#define CMDRSP1 0x2e014
-#define CMDRSP2 0x2e018
-#define CMDRSP3 0x2e01c
+/* eSDHC_IRQSTAT register: 0x00000030 */
+#define IRQSTAT_DMAE 0x10000000
+#define IRQSTAT_AC12E 0x01000000
+#define IRQSTAT_DEBE 0x00400000
+#define IRQSTAT_DCE 0x00200000
+#define IRQSTAT_DTOE 0x00100000
+#define IRQSTAT_CIE 0x00080000
+#define IRQSTAT_CEBE 0x00040000
+#define IRQSTAT_CCE 0x00020000
+#define IRQSTAT_CTOE 0x00010000
+#define IRQSTAT_CINT 0x00000100
+#define IRQSTAT_CRM 0x00000080
+#define IRQSTAT_CINS 0x00000040
+#define IRQSTAT_BRR 0x00000020
+#define IRQSTAT_BWR 0x00000010
+#define IRQSTAT_DINT 0x00000008
+#define IRQSTAT_BGE 0x00000004
+#define IRQSTAT_TC 0x00000002
+#define IRQSTAT_CC 0x00000001
-#define DATPORT 0x2e020
+#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+ IRQSTAT_DMAE)
+#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
-#define WML 0x2e044
-#define WML_WRITE 0x00010000
+/* eSDHC_IRQSTATEN register: 0x00000034 */
+#define IRQSTATEN_DMAE 0x10000000
+#define IRQSTATEN_AC12E 0x01000000
+#define IRQSTATEN_DEBE 0x00400000
+#define IRQSTATEN_DCE 0x00200000
+#define IRQSTATEN_DTOE 0x00100000
+#define IRQSTATEN_CIE 0x00080000
+#define IRQSTATEN_CEBE 0x00040000
+#define IRQSTATEN_CCE 0x00020000
+#define IRQSTATEN_CTOE 0x00010000
+#define IRQSTATEN_CINT 0x00000100
+#define IRQSTATEN_CRM 0x00000080
+#define IRQSTATEN_CINS 0x00000040
+#define IRQSTATEN_BRR 0x00000020
+#define IRQSTATEN_BWR 0x00000010
+#define IRQSTATEN_DINT 0x00000008
+#define IRQSTATEN_BGE 0x00000004
+#define IRQSTATEN_TC 0x00000002
+#define IRQSTATEN_CC 0x00000001
+
+/* eSDHC_WML register: 0x00000044 */
+#define WML_WRITE 0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
#define WML_RD_WML_MAX 0x80
#define WML_WR_WML_MAX 0x80
@@ -151,17 +133,18 @@
#define WML_WR_WML_MASK 0xff0000
#endif
-#define BLKATTR 0x2e004
-#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
-#define BLKATTR_SIZE(x) (x & 0x1fff)
-#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+/* eSDHC_HOSTCAPBLT2 register: 0x00000114 */
+#define HOSTCAPBLT2_VS18 0x04000000
+#define HOSTCAPBLT2_VS30 0x02000000
+#define HOSTCAPBLT2_VS33 0x01000000
+#define HOSTCAPBLT2_SRS 0x00800000
+#define HOSTCAPBLT2_DMAS 0x00400000
+#define HOSTCAPBLT2_HSS 0x00200000
+
+/* eSDHC_ESDHCCTL register: 0x0000040c */
+#define ESDHCCTL_PCS 0x00080000
-#define ESDHC_HOSTCAPBLT_VS18 0x04000000
-#define ESDHC_HOSTCAPBLT_VS30 0x02000000
-#define ESDHC_HOSTCAPBLT_VS33 0x01000000
-#define ESDHC_HOSTCAPBLT_SRS 0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
-#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#define PIO_TIMEOUT 500
struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
@@ -173,7 +156,7 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if defined CONFIG_SYS_FSL_ESDHC_LE
+#if defined(CONFIG_SYS_FSL_ESDHC_LE)
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
2.7.4
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