[U-Boot] [PATCH] net: zynq_gem: Remove check for Versal

Michal Simek michal.simek at xilinx.com
Wed Sep 11 08:42:21 UTC 2019

From: Siva Durga Prasad Paladugu <sivadur at xilinx.com>

This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>

This patch depends on https://lists.denx.de/pipermail/u-boot/2019-September/383239.html

Joe: I would take this together with versal clock driver when reviewed.
 drivers/net/zynq_gem.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a35ecab79ee9..a7a6ce987f07 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
-#if !defined(CONFIG_ARCH_VERSAL)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
-	debug("requested clk_rate %ld\n", clk_rate);
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |

More information about the U-Boot mailing list