[U-Boot] [PATCH 1/4] arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX

Rasmus Villemoes rasmus.villemoes at prevas.dk
Thu Sep 12 09:17:09 UTC 2019


I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes at prevas.dk>
---
 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h |  6 ++++--
 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 15 ++++++++++-----
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
index 6e9ffeb6d5..50fdc9cd03 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -24,8 +24,10 @@ struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
 	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
 	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
-	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
-	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
+	uint32_t	hw_clkctrl_ssp0;	/* 0x70 */
+	uint32_t	reserved_ssp0[3];	/* 0x74-0x7c */
+	uint32_t	hw_clkctrl_gpmi;	/* 0x80 */
+	uint32_t	reserved_gpmi[3];	/* 0x84-0x8c */
 	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
 	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
 
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index 01e0a7a053..caef9e4b1f 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -27,11 +27,16 @@ struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
 	mxs_reg_32(hw_clkctrl_xbus)		/* 0x70 */
 	mxs_reg_32(hw_clkctrl_xtal)		/* 0x80 */
-	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
-	mxs_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
-	mxs_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
-	mxs_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
-	mxs_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
+	uint32_t	hw_clkctrl_ssp0;	/* 0x90 */
+	uint32_t	reserved_ssp0[3];	/* 0x94-0x9c */
+	uint32_t	hw_clkctrl_ssp1;	/* 0xa0 */
+	uint32_t	reserved_ssp1[3];	/* 0xa4-0xac */
+	uint32_t	hw_clkctrl_ssp2;	/* 0xb0 */
+	uint32_t	reserved_ssp2[3];	/* 0xb4-0xbc */
+	uint32_t	hw_clkctrl_ssp3;	/* 0xc0 */
+	uint32_t	reserved_ssp3[3];	/* 0xc4-0xcc */
+	uint32_t	hw_clkctrl_gpmi;	/* 0xd0 */
+	uint32_t	reserved_gpmi[3];	/* 0xd4-0xdc */
 	mxs_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
 	mxs_reg_32(hw_clkctrl_emi)		/* 0xf0 */
 	mxs_reg_32(hw_clkctrl_saif0)		/* 0x100 */
-- 
2.20.1



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